PYNQ: PYTHON PRODUCTIVITY FOR ZYNQ

Ported my working Pynq2.4 project to Pynq 2.5 and it nows crashes on VDMA read

Hi there,

Any one have issues with VDMA engines in Pynq 2.5.
I ported a working project from 2.4 (Ultra96) to 2.5 (ZCU102), also migrating to vivado 19.1.

Setting up the VMDA driver

PL_vdma = overlay.axi_vdma_0
framemode = VideoMode(1280, 720, 24)

Set the read channel parameters to the capture specifications and enable the VDMA

PL_vdma.readchannel.mode = framemode

I have a couple of selectable axi stream swtiches

Set for normal passthrough

set_path_pipeline(1)

set to test pattern

set_source_pipeline(2)
PL_vdma.readchannel.start()
frame_tp = PL_vdma.readchannel.readframe()
PL_vdma.readchannel.stop()
frame_color_tp=cv2.cvtColor(frame_tp,cv2.COLOR_BGR2RGB)
pixels_tp = np.array(frame_color_tp)
plt.imshow(pixels_tp)
plt.show()

set to webcamera source

set_source_pipeline(1)

As soon as i call PL_vdma.readchannel.start() Pynq and the entire board crashes / stalls. Any idea what the problem might be.

See attached notebook as well…

Darth

video_pipeline-8.ipynb (22.9 KB)

I am guessing (only guessing) it might be the PS configurations differ from the 2 versions. Maybe you can check the AXI port width for your old image and the new image. When you download bitstream, the PS configuration does not get changed (except the PL clocks).

e.g. check Register(0xFF419000)[9:8] to see if they are the same.

I have a simple adder ip block and it works ok.

I did tweak things a bit, like the address space for the vdma blocks, now that theres is 4GB of DDR4 vs 2GB on the Ultra96.

I think you might check the 2 tcl files that are used to generate the block design, or the PS configuration in your block design. Double check the memory port (enabled or not, port width) to make sure they are correct. Also find the PS configuration in the ZCU102 bsp, and make sure the configuration is correct; this is because the PYNQ image always uses the PS configurations from the petalinux bsp after boot. If not, you may need to adjust some register values.

HI Rock,

Managed to get it working by replicating the memoroy space for the Ultra96 and not defined memroy segment HP0_DDR_HIGH. I also limited the VDMA address bits to 32bits…

Darth

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