The 142 MHz clock is not the pixel clock. The pixel clock is separate.
If this clock is slower than the pixel clock, you need a bigger FIFO (in the AXI stream to video IP), so increasing this clock might make it harder to close timing, but you should/may be able to reduce buffer. I wouldn’t do this. I think this was set to this freq as the minimum to process 1080p data without the sync and blanking periods, but open to correction on this.
The pixel clock is generated from the Dynamic clock generator. For the speedgrade used in the Zynq chip for this board (-1), 1080p is outside the spec for the IO. The spec is for worse case which is why you might see 1080p works for some people on the forums, and not the others. i.e. there will be variation between chips, and most boards are running at room temperature, not at corner case temperatures. I find some equipment is more sensitive. E.g. One monitor may work, another may not with the same board. According to the spec, the board can only meet 720p.
1080p may be OK for playing around with, or for hobbyists - if it works with your equipment, but you wouldn’t use this Zynq chip for a commercial application @1080p. Perhaps think about this as overclocking.