PYNQ: PYTHON PRODUCTIVITY FOR ZYNQ

Taking over control of displayport output using live feed settings

Hi all,

My setup:
Pynq 2.4
Ultra96V1 (Ultrascale Zynq)

Im basically trying to use the xilinx test pattern generator and timing controller to show color bars on the displayport output of the device.

I following Adam Taylors recipe to do this with some additions (like an adder HLS block just to test axi read/writes).

I then followed the recipe to for poking the tgp and vtc blocks according to:

tpg = overlay.v_tpg_0
vtc = overlay.v_tc_0
tpg.write(0x10,720)
tpg.write(0x18,1280)
tpg.write(0x40,0)
tpg.write(0x20,9)
tpg.write(0x00,0x81)
vtc.write(0x00,0x01) <- this is the go signal

I set the tpg output to be the same as that dervived by the tpg & vtc, i.e. 1280x720. Theres a 74.25MHz pixel clock in the FPGA fabric to do this.

Heres what i have checked:

  • blocks are bound in correctly
  • i can peek and poke the blocks (proving memory mapping is correct)
  • double checked registers for setting vtc and tpg against drivers and xilinx documentation.

Issue is that the chromium desktop has remained. There is not sign of the colour bars.

Has anyone trying to use the PL fabric to control the hard displayport section of the Ultrascale ZYnq part?

Thanks,

Darth