PYNQ: PYTHON PRODUCTIVITY

Vitis vision core fails on PYNQ V2.5.1

I checked my IP:
image

It looks like TLAST is available for both src and dst. My HLS code is below:

#include "xf_axis_config.h"
#include "xf_pyr_down_config.h"


void axis2xfMat(axis_t* src, 
			   xf::cv::Mat<TYPE, HEIGHT, WIDTH, NPC_T>& img) {
	int rows = img.rows;
	int cols = img.cols;
	int idx = 0;

	for (int i = 0; i < rows; i++) {
		for (int j = 0; j < cols; j++) {
			// clang-format off
    		#pragma HLS loop_flatten off
    		#pragma HLS pipeline II=1
			// clang-format on
	        img.write(idx++, src->data);
			src++;
		}
	}
}


void xfMat2axis(xf::cv::Mat<TYPE, HEIGHT, WIDTH, NPC_T>& img,
				axis_t* dst) {
	int rows = img.rows;
	int cols = img.cols;
	int idx = 0;

	for (int i = 0; i < rows; i++) {
		for (int j = 0; j < cols; j++) {
			// clang-format off
    		#pragma HLS loop_flatten off
    		#pragma HLS pipeline II=1
			// clang-format on
			ap_uint<1> tmp = 0;
			if ((i==rows-1) && (j== cols-1)) {
				tmp = 1;
			}
			dst->last = tmp;
			dst->data = img.read(idx++);
			dst++;
		}
	}
}


extern "C" {
void pyrdown_accel(axis_t* src,
				   axis_t* dst,
                   int in_rows,
                   int in_cols,
                   int out_rows,
                   int out_cols) {
// clang-format off
    #pragma HLS INTERFACE axis port=src
    #pragma HLS INTERFACE axis port=dst
    #pragma HLS INTERFACE s_axilite port=in_rows     
    #pragma HLS INTERFACE s_axilite port=in_cols     
    #pragma HLS INTERFACE s_axilite port=out_rows     
    #pragma HLS INTERFACE s_axilite port=out_cols     
    #pragma HLS INTERFACE s_axilite port=return
// clang-format on

    xf::cv::Mat<TYPE, HEIGHT, WIDTH, NPC_T> in_mat(in_rows, in_cols);
// clang-format off
    #pragma HLS stream variable=in_mat.data depth=150
// clang-format on

    xf::cv::Mat<TYPE, HEIGHT, WIDTH, NPC_T> out_mat(out_rows, out_cols);
// clang-format off
    #pragma HLS stream variable=out_mat.data depth=150
// clang-format on

// clang-format off
    #pragma HLS DATAFLOW
// clang-format on
    axis2xfMat(src, in_mat);	
    xf::cv::pyrDown<TYPE, HEIGHT, WIDTH, NPC_T, XF_USE_URAM>(in_mat, out_mat);
    xfMat2axis(out_mat, dst);
}
}

My config header:

#ifndef _XF_AXIS_CONFIG_
#define _XF_AXIS_CONFIG_

#include <iostream>
#include <math.h> 
#include "hls_stream.h"
#include "ap_int.h"
#include "common/xf_common.hpp"
#include "imgproc/xf_pyr_down.hpp"
#include "xf_config_params.h"

struct axis_t {
    ap_uint<8> data;
    ap_int<1> last;
};

void pyrdown_accel(axis_t* src,
					axis_t* dst, 
                    int in_rows,
                    int in_cols,
                    int out_rows,
                    int out_cols);
#endif

Thank you for such a quick reply. I have implemented your code without any change in Vitis HLS 2020.1, it shows this error:

ERROR: [HLS 207-2542] declaration of 'pyrdown_accel' has a different language linkage: pyr_down/pyrdown_accel.cpp:49:54
INFO: [HLS 207-70] previous declaration is here: pyr_down/xf_axis_config.h:17:6

So I have commented out the function line in header files.
//void pyrdown_accel(axis_t* src,axis_t* dst, int in_rows, int in_cols, int out_rows, int out_cols);

it generates the IP without TLAST.

image

Hi @rock ,
Have you used Vitis HLS to generate the IP? or Vivado HLS 2019.2. Because in Vivado HLS 2019.2, it’s working fine. But in Vitis HLS 2020.1, no luck so far.

Also, even tlast is generated in 2019.2, still in PYNQ it stuck at DMA receiver side for resizer IP. I have tried with testbenches, it works flawlessly, so I just made another controller IP to control the IP from PYNQ.

It would be great if you could suggest some solution for Vitis HLS 2020.1.

I don’t know your issue, but as I mentioned above, with my suggested changes, I was able to generate the IP with TLAST. You should not need to comment anything in the header.

Don’t need to be rude. I was just asking if you used the vitis hls or not. Sorry for both giving you trouble and putting you in header.

:slight_smile: I meant “you should not comment out any code in the header”.

If possible, can you paste your entire .cpp/.h file so I can take a look?

1 Like

My apologies, I didn’t understand you correctly.
I just exactly copied your code for pyrDown and tried to generate the IP in Vitis HLS 2020.1. I changed nothing at all. It was showing the error in the header file for mentioned error. If I delete/comment it out, it generates the IP without any error, but Tlast doesn’t show up.
I think if you try with Vitis hls 2020.1, you will face the same error, as in both windows and ubuntu I am having the same result.

Also a few days back, I tried with Vivado HLS 2020.1 (which should be run from the command line interface), I had to comment out (iostream header file) and edited some lines in the library code. It was generating the core with Tlast. No problem with both PYNQ and PL testing. But most of Vision library functions shows lots of error with Pragmas and variables (in Vision library include files) in Vivado HLS (which must be handled before generating the IP). I have synthesized some of them and tested them. those are running fine.

Now I am trying to implement the undist function for correcting lens distortion. As usual there are errors showing up in vivado hls, which doesn’t show up in Vitis HLS.

A lot of work here, thank you for digging in. I had the same problem the last weeks and @rock forwarded me here.

I tried the same using hls::stream and ap_axiu (code in the comments of Update HLS IP to build on 2020.2 by giunatale · Pull Request #24 · Xilinx/PYNQ-HelloWorld · GitHub).

I see that the problem could be solved by rewriting axis2mat and mat2axis functions.

Still I would like to use the convenience functions already provided (and recommended) by Vitis. As far as I understand xf::cv::ap_axiu from xf_axi_sdata.hpp should not be used until it is fixed in next release, but the version in ap_axi_sdata.hpp should work. I will try synthesizing using the ap_axiu from the ap_axi_sdata.hpp.

Update:
I saw that xf::cf::ap_axiu was already removed in December (Squashed 'vision/' changes from e6c9cad..bfd1d41 · Xilinx/Vitis_Libraries@915899b · GitHub). So I was using the right ap_axiu.

I would be happy if someone figured out the solve this problem using hls::stream and ap_axiu like I tried in my above link.

@rock I used your template, but I also get an interface without tlast and only 8 bit tdata even I specify 24 bit width like @mizan. You can find my project here:

image-resizer-using-axis_t

try the same code with Vivado HLS 2020.1 (run it from command prompt). It will generate the core and works properly (you might need to take care of some PIPELINE and DATAFLOW pragma errors).

I am looking for a solution with the newest Vitis. Thanks @mizan :slightly_smiling_face:

1 Like

Hey @leuko, have you found one?

No :frowning:

The work on that seem to be stalled: Update HLS IP to build on 2020.2 by giunatale · Pull Request #24 · Xilinx/PYNQ-HelloWorld · GitHub

Instead of that I showed a memory-mapped solution to my students:

1 Like

Hi @leuko,

Have you tried to use the 8 pixels per word mode on your Memory-mapped image resizer version? Or do you have any clue of the modification that need to be done during Vivado design/notebook implementation?

Thank you

I did not try. I would try by setting the resource optimized (RO) to 1 and normal operation (NO) to 0.

good luck!