AP_DONE is always zero!

Hello,
I have a design with the following top level function in HLS:

int run(uint32_t pc,  uint64_t &cycle, uint64_t &instruction_counter, uint64_t rom[Rom_SIZE], uint32_t ram[SIZE]) {
#pragma HLS INTERFACE mode=s_axilite port=return bundle=ctrl
#pragma HLS INTERFACE mode=s_axilite port=pc
#pragma HLS INTERFACE mode=s_axilite port=instruction_counter
#pragma HLS INTERFACE mode=m_axi port=rom bundel=rom
#pragma HLS INTERFACE mode=m_axi port=ram bundel=ram
...
}

And here is the block design:

In pynq after feeding the input of the IP block, I start the Ip:

my_ip.write(0x00,0x81) 

Then I check to see if the Ip is done, but it gets stuck:

while(my_ip.register_map.CTRL.AP_DONE == 0):
    pass

Does anybody know what the problem is?
Thanks in advance

Can you share which version(s) of software you are using? Vivado, Vitis, PYNQ?
Are you sure your function completes? Can you share the rest of your code?

Cathal

Thanks @cathalmccabe for your response.
I’m using Vitis and Vivado 2022.2 and the pynq image version 3.0.1.
Yes, I’m sure that the function completes, it’s a simple riscv processor. There is a while loop in which one instruction is read from rom memory and executuded in each iteration.

while(true){
#pragma HLS PIPELINE II=1
    if(instruction != RET){
            instruction = rom[PC];
           //execute the instruction
           PC = next_pc;
   }
   else
        break;
}