I try to run a very simple program on ZCU104 to test the PYNQ design process, my program stuck there when I trying to start the overlay, here are the details:
1.Evaluation Kit: EK-U1-ZCU104-G-ED
2.Detail Information
2.1 In Vivado HLS, write a basic program, which only reads in a matrix with 28*28 8-bit elements, change the matrix elements value, then return the revised matrix.
Here is the HLS function code:
When validating the block design, the memory address cannot be located correctly.
I have to choose “Auto Assign Address” in the address editor, but some ports are still excluded and left critical warning here.
My program stuck hanging here:
" if(ap_done):
print(mmio.read(ADDR_AP_CTRL))
break"
since ADDR_AP_CTRL always be 0.
I do a small test, assign values to different IP addresses.
For those pre-claimed registers, no matter what value I assign, the value is always 0, I guess this is the direct cause of the problem, but not where I should fix it.
For the self-claimed memory address, I can correctly write in the value(cc=0x81=129).
.Can anyone give me some advice? A thousand thanks.
Try to give the .bit and .hwh files the same names (i.e. NAME.bit and NAME.hwh).
Try to export the .tcl file from Vivado and put it on the board besides the .bit and .hwh files (also use the same name NAME.tcl).
From your Vivado integration diagram I don’t see that you’re using any interrupt. Try to comment out any part of your code that deals with GIE or IER … probably they’re making some troubles.
In your StartStop_Ex(state) method, try to check whether the IP is idle before you ask it to execute … something like:
# Check if IP is idle
while(True) :
bits = mmio.read(ADDR_AP_CTRL)
ap_idle = bits>>2 & 0x1
if ap_idle == 1:
break
# IP is idle and ready to compute .. do your business
In your IPI diagram, it looks like you haven’t connected ap_ctrl, and it isn’t an AXI interface.
As it isn’t an AXI interface, you can’t use MMIO.
As it isn’t connected, you can’t control this IP at all
In your HLS, you haven’t specified anything for your control interface, so you get a default ap_ctrl port. This will generate an interface of wires that you need to connect to your design in some way.
It is better to use an AXI lite interface for the control port:
#pragma HLS INTERFACE s_axilite port=return
You can bundle the control and the input addresses for the arrays to the same AXI slave interface.
You then need to check the address offsets in your code for the updated design.
As far as I understand, the input port for the array requires m_axi port, the return port for CTRL uses s_axilite port, how can I simply bundle them together?
The updated block diagram here:
I have such 4 critical warnings but don’t know what to do, so I just ignore them.
In the Pynq, I updated the execution function with ap_idel check.
Before execution, print(mmio.read(ADDR_AP_CTRL)) returns value 4, which means ip_idle=1; After execution, print(mmio.read(ADDR_AP_CTRL)) returns value 131!!!
Seems that my overlay won’t be stuck here!!! (in the past, the ap_idle never be 1, so the overlay will be stuck on this execution step)
The new problem is, the ADDR_OUTBUFFER has no output value update.
However, I don’t know which step was wrong. (FPGA not working, or only output not transferred to RAM?)
I tested it by adjusting the clock_wizard IP blcok’s output frequency, from 100MHz to 10MHz
I record the time before/after execution as the figure shows in step4, find out that the execution time doesn’t change under 100Mhz/10Mhz, which means the FPGA is not running?
