AXI Burst need support on Pynq Z1/Z2 with Vitis HLS rather than merely Vivado HLS

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Thanks for recommending YouTube link Using the PYNQ ‘register map’ functionality. I test register map and it works well (same result as the the way in axi4):

image
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part of Code:

AF_interface_ip.register_map
AF_interface_ip.register_map.len = 7
length = 7
inpt = Xlnk().cma_array(shape=(length,), dtype=np.float32)
outpt = Xlnk().cma_array(shape=(length,), dtype=np.float32)
# a = [1.272, 0.675, 2.479,1.06,1.16,1.11, 1.11] # outpt[0] == 0
a = [-0.074,1.59,-2.251,0.575552,1.115450,0.657046,0.589000]   # outpt[0] == 1
np.copyto(inpt, a)
AF_interface_ip.register_map.in_r = inpt.physical_address
AF_interface_ip.register_map.out_r = outpt.physical_address
AF_interface_ip.register_map.CTRL.AP_START=1

Test Version: Vivado (HLS) 2019.1. I use it simply test register map function, I will test newer version later: )

These two links also help me:
Pynq to m_axi HLS IP
PYNQ_tutorials/hls_m_axi /hls_m_axi_example.ipynb

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