AXI burst size in Pynq Z2 vs Vitis HLS

[briansune]

@davide-giacomini

I had mentioned:
There is a structure in the header or define section to defines the interfaces of the function passing I/O.
Look for it and you can also find a AXI-Stream tutorial here or online.

For example in MNIST CNN design:

MNIST + AXI Stream on PYNQ 2.7 (Attention to Details)

Hello PYNQ community: I wish you all doing great =] Previous support posts are having trouble on AXI stream HLS about CNN design and DMA: So I am going to share the details on 2020.2 HLS tool and PYNQ 2.7 design. The Github Repository Link for this tutorial: HLS AXI Stream People keep asking about tlast is missing, which this is common that after version (not sure when) the structure C no longer interpret as we expected: Old struct AXI_DMA_IO{ ap_int<16> data; ap_int<1>last; }; New …

ENJOY~