DMA issue that might be due to software initialization I think this is a PYNQ problem, not a Xilinx problem. What I have is a very simple design with the ZYNQ block, connected to 2 DMA blocks. One of the blocks reads from DDR and streams into an AXI fifo (so only the READ port is enabled), the o…

Hmm, maybe it’s actually ok. Here’s what Claude.ai says (either it’s ok or Claude was just telling me what it thinks I wanted to hear!): Looking at your AXI DMA control register value of 0x10003, this appears to be the expected default state for an AXI DMA after loading the bitstream. Let me break…

I asked Claude.ai for the documentation that says that the initialization should be with 0x10003 in the control register, and it apologized and said it could not find such documentation. I should have been clearer in describing what I see. So if I have 1 DMA engine with both MM2S and SS2M enabled…

Hi @drewphysics , I am trying to understand what is the issue. Are you having a problem when running the data movement? Or would you like to understand the registers? I suggest you use the PYNQ register_map feature, so it is easier to decode the registers. You are also looking and old version of t…

[image] marioruiz: AMD Technical Information Portal Hi Marioruiz, thanks for your reply and link. I guess what I’m really curious is the following: in my python code, I get the base pointer from the Overlay() function. My AXI DMA engine is named “AXI_DMA”. so when I issue the command d…

Hi Drew, The DMA user guide should give you the information to the DMA registers. As per your code. I would say that the first transaction never finished. This is likely why you get the halt bit and the `DMA channel not started`. Without seeing the block design, it is hard to say what could be wr…

Thanks for your comments! I checked with a .wait() and it came back finished immediately. This is as expected since it was only 100 words of 4 bytes each. Here is the project. the AXI_DMA module is configured to not have scatter-gather enabled, and the buffer length register is set to 26 but o…

Hi @drewphysics , I do not have a great answers to your questions. I may suggest you post them in the Xilinx forums. Another suggestion will be to use independent DMAs for each channel. Mario

Thanks, separate DMA engines is a good idea. I tried it and I get the same errors when reading the FIFO. I then made the buffers the same size, doing a DMA write 100 words into the FIFO, and then DMA read 100 words back into DDR. When I then look at the control and status registers, I see no er…

I built a project with the System ILA. In the following, the top 5 signals are from the MM2S channel that writes into the AXI FIFO, and the next 5 are from the S2MM channel that reads from the FIFO. This first picture is from sending 100 words into the FIFO. Each word has 0xcafe in the upper 16 b…

AXI DMA puzzle (maybe)

Support

marioruiz August 8, 2025, 5:24pm 10

It could be because the 10 word transaction does not have TLAST.

You can try to add an IP (AXI4-Stream Subset Converter) to assert TLAST after 10 transactions.

Topic		Replies	Views
Debugging Common DMA Issues [Part 3] Learn	10	1924	August 25, 2025
Tutorial: PYNQ DMA (Part 2: Using the DMA from PYNQ) Learn	7	20837	May 27, 2025
Tutorial: PYNQ DMA (Part 1: Hardware design) Learn	35	40659	October 11, 2025
AXI DMA not working on PYNQ-Z1 Support	12	5875	February 8, 2023
Getting "RuntimeError: DMA channel not started" occasionally Support	19	3445	February 22, 2023

AXI DMA puzzle (maybe)

Related topics