Hey there,
I’m using PYNQ-Z2 board, built my IP with Vitis HLS - a bruteforcer.
There are two interfaces- the CTRL_BUS is using AXI-Lite and the progress is using AXI-Stream.
In the main loop I’m streaming i to the progress and co-simulation shows everything works.
When loading the overlay into PYNQ and starting the IP, the logic in the IP works and performs the bruteforce as expected, while the progress stays 0.
The main code in the IP:
void bruteforce(const unsigned int md5bf[4], const unsigned char charset[CHARSET_LENGTH], unsigned char out[LENGTH], int &found, hls::stream<progress_t> &progress)
{
#pragma HLS INTERFACE axis port=progress
#pragma HLS INTERFACE s_axilite port=md5bf bundle=CTRL_BUS
#pragma HLS INTERFACE s_axilite port=charset bundle=CTRL_BUS
#pragma HLS INTERFACE s_axilite port=out bundle=CTRL_BUS
#pragma HLS INTERFACE s_axilite port=found bundle=CTRL_BUS
#pragma HLS INTERFACE s_axilite port=return bundle=CTRL_BUS
unsigned int md5bf_reversed[4];
for (int i=0; i<4; i++) {
md5bf_reversed[i] = reorderBytes(md5bf[i]);
}
found = 0;
unsigned char current[LENGTH];
for (int i = 0; i < LENGTH; i++)
{
current[i] = charset[0];
}
int n = CHARSET_LENGTH;
int k = LENGTH;
ap_uint<32> max_iterations = compute_permutations_with_repetition(n, k);
for (ap_uint<32> i = 0; i < max_iterations; i++)
{
// Send progress data
progress_t progress_data;
progress_data.data = i;
progress_data.last = (i == max_iterations-1) ? 1 : 0; // Signal the end of the stream
progress.write(progress_data);
char padded[BUFFER_SIZE];
unsigned int padded_size;
copy_pad(padded, current, LENGTH, padded_size);
unsigned int md5out[4];
md5((unsigned int*)padded, md5out, padded_size);
bool match = true;
for (int i=0; i < 4; i++) {
if (md5bf_reversed[i] != md5out[i]) {
match = false;
break;
}
}
if (match)
{
copy_uchar(out, current, LENGTH);
found = 1;
break;
}
bool carry;
generate_next_combination(carry, current, charset);
if (carry) {
break;
}
}
}
co-simulation in Vitis HLS waveform shows progress data as expected over time.
In the PYNQ Jupyter I’m running
overlay = Overlay('my_overlay.bit')
size = 1
# Create a contiguous memory buffer to hold data
output_buffer = allocate(shape=(size,), dtype=np.uint32) # change size and dtype accordingly
dma = overlay.axi_dma # replace with your DMA's name
dma.recvchannel.transfer(output_buffer) # Receiving streamed output
No errors or anything and IP would perform the task as expected, returned through the AXI-Lite interface, but when reading output_buffer it contains 0 and would not change.
Would highly appreciate any advice you might have on why the progress would not update.
Thank you!