Zynq AXI HP Interface

Hi everyone!
I am using Pynq-Z2 board along with Version 2020.2 of Xilinx design tools.

I have created a custom IP in Vitis HLS to perform multiplication operation between two arrays w and x . The arrays have been passed as a pointer with m_axi mode. The HLS code is attached in the following image.

After exporting the RTL, I add it to Vivado. Then a new block diagram is created where I add Zynq and the custom IP which I have created. After running connection automation, I get the following warnings. I have enabled HP0 and GP0 interfaces under PS-PL configuration in Zynq block. Could anyone please tell how can we resolve the following addressing issues.

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The warning is indicating a problem with your address map. Did you check this? There should be a tab for this beside the tab for you block design.
Adding more info and proper screenshots would help.


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