Building a daq from RFSoC 4x2?

[zeckjia]

Hello,

I’m trying to build a daq from RFSoC 4x2. I have read and gone through a lot of tutorials on this Forum (and thank you for your effort in supporting this community!!).

Here is information of the PYNQ and board I’m using:
PYNQ version: 2.7.0
Board: RFSoC 4x2

My current strategy is streaming data from ADC to PS DRAM using DMA, then transfer data from PS DRAM to my computer via either PS ethernet or USB 3.0 ports. I have built the hardware design (bitstream, Tcl, and hwh files are attached in “daq.zip”). I have copied the bit, tcl, and hwh files to the board. But I’m a little confused in how to use iPython Notebook to stream data. Did I miss some steps after building the hardware? Could you please give me some advice on what I could do for next step? Or Are there any tutorials I may have missed within this forum?

Thank you in advance for your help!

Regards,
zeckjia

daq.zip (542.1 KB)

[marioruiz]

Hi @zeckjia,

In the Learn section there are a few tutorials.

I recommend you check out these two to create designs that use DMA (note that they have multiple parts)

Tutorial: PYNQ DMA (Part 1: Hardware design)

PYNQ DMA tutorial (Part 1: Hardware design) This tutorial will show you how to use the Xilinx AXI DMA with PYNQ. It will cover adding the AXI DMA to a new Vivado hardware design and show how the DMA can be controlled from PYNQ. This tutorial is based on the v2.6 PYNQ image and will use Vivado 2020.1. If you are using a different PYNQ version you should be able to follow the same steps in this tutorial, but you should make sure you are using the supported version of Vivado for that PYNQ release. …

Tutorial: using a HLS stream IP with DMA (Part 1: HLS design)

Tutorial: using a HLS stream IP with DMA tutorial (Part 1: HLS design) In a previous tutorial I showed how to use the AXI DMA to stream data between memory to AXI stream interfaces. The DMA tutorial used an AXI stream FIFO to do a loopback test to show how to use the DMA. This tutorial will show how to create and add a HLS IP with an AXI input stream, and AXI output stream. This tutorial will be split into two parts. This part 1 shows how to build the HLS IP, part 2 shows how to build the Vivad…

Mario

[zeckjia]

Hi Mario,

Thanks for your reply! Indeed I followed the two tutorials you posted to build my design (and thank you for confirming that I followed the right path!). But I’m not currently using any self-built HLS streaming IP. Major IPs I used include Zync US+ RF Data Converter, AXI DMA, and of course Zync US+ MPSoC.

To be clear, I’m not sure if I need to write divers for my overlay if I don’t have any self-built HLS streaming IP. Could you please help me clarify this? It may be easier for you to see my overlay if I include the block design here:

Besides, bitstream, Tcl, and hwh files can be found in “daq.zip” in my original post. Thank you so much for your help!

zeckjia

[marioruiz]

Hi @zeckjia,

I don’t fully understand what you’re asking.

The posts I shared include the Python code to use the DMA module to bring data into the PS. You don’t need to write a driver unless you want to add functionality that doesn’t exist in the default driver.

Have you written any code to bring in the data via the DMA?

Mario

[zeckjia]

Hi Mario,

Thanks for your reply! I think I understand how to use DMA to bring data into the PS. But I don’t know how to read the data from the outside world into PL using the RF Data Converter module.

If you see my block design above, I have an RFDC module (only one ADC enabled) connected to DMA via an FIFO. Basically, I don’t know how to control this RFDC module in PYNQ. Could you please give me some help on this? Thanks!

zeckjia

[marioruiz]

Hi @zeckjia,

I may suggest you review the Software Define Radio with Zynq UntraScale+ RFSoC book, you will find this information there.

You can also refer to the IP user guide.

Mario

[zeckjia]

Thanks, Mario! I will look into the book and the IP user guide!