PYNQ: PYTHON PRODUCTIVITY

Building PYNQ image for ZCU111 w/ 2019.2 or 2020.1

We needed to migrate to 2019.2 to fix some issues with the xilinx vector blockset and vector Vitis HLS. I’m starting to suspect (as I’ve posted elsewhere here) that this has resulted in bitstreams that aren’t properly supported by the 2.5 image with the pynq package upgraded to 2.5.4 (specifically relating to the rf data converter block).

To test this I’m trying to build a board image using 2019.2, but the more I read about it I’m unclear if this is supported. My plan was to follow the SD card build guide with the ZCU111 board files from https://github.com/Xilinx/ZCU111-PYNQ. Probably trying to use the 2.5.6 image branch and the pynq 2.6.0 image branch in hopes that that helps with compatibility. My understanding is that i do NOT need the zcu111 bsp that is part of petalinuz 2019.2, correct?

@PeterOgden I’m seeing that you’ve got some active work on these branches, anything I should know?

I have seen somewhere that v2.6.0 image will be released in like 2-3weeks.
You could try to build PYNQ with raw petalinux like this Deploying PYNQ and Jupyter with Petalinux.

I’ve managed to get an Ubuntu VM setup for building, this proved a bit of a process. After first starting with 2019.2 and the 2.6 branches for PYNQ and the ZCU111 I quickly discovered that those branches expect 2020.1. Vitis 2020.1 continues to be a fraught process due to (I suspect) either installer screen display detection code when Ubuntu is in a Parallels VM or the Ubuntu 18.04.5 security point release (18.04.4 is the officially supported OS). By following the command line install here I got 2020.1 installed.

Using the readme files for pynq sdbuild and the ZCU111 I’ve managed to make to start an image build but it fails. In the first phase there are a few dpgk errors and a pip error relating to a plotly-express error:

ERROR: After October 2020 you may experience errors when installing or updating packages. This is because pip will change the way that it resolves dependency conflicts.

We recommend you use --use-feature=2020-resolver to test your packages with the new resolver before it becomes the default.

plotly-express 0.3.1 requires plotly<4.0.0a0,>=3.10.0, but you’ll have plotly 4.5.2 which is incompatible.

When it starts building bitstreams though it finally dies:
Command: write_bitstream -force base_wrapper.bit

Attempting to get a license for feature ‘Implementation’ and/or device ‘xczu7ev’
INFO: [Common 17-349] Got license for feature ‘Implementation’ and/or device ‘xczu7ev’
INFO: [Common 17-83] Releasing license: Implementation
369 Infos, 254 Warnings, 9 Critical Warnings and 1 Errors encountered.
write_bitstream failed
ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst ()
base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst ()
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.
INFO: [Common 17-206] Exiting Vivado at Wed Oct 7 14:09:50 2020…
[Wed Oct 7 14:09:51 2020] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : ‘impl_1’

ERROR: [Common 17-70] Application Exception: Need an implemented design open to write bitstream. Aborting write_hw_platform…

Which I gather is due to a licensing issue with HDMI, so I’ll try and go sort that out.

Is there a way to make it skip building bitstreams for the other boards to save time? I used the command make BOARDDIR=/home/parallels/2020.1/ZCU111-PYNQ but I’m still seeing it plow through other boards like the zcu102.

Building one board works only for me if I go to sdbuild and “make BOARDS=<board_name_in_boards_directory” for example “make BOARDS=Pynq-Z2” This is working on v2.5.1 image.
If you have HDMI issues look at ZCU104. spec file and you will see .bsp specified.
Download that .bsp from Xilinx website and copy to ZCU104 folder. It will solve licensing issues.
You could use this but note this is still work in progress and tested with Digilent Eclypse-Z7. But it should show you what do you need to build your custom board

Hmm, thanks. I did not download the BSPs for the bords in PYNQ/boards, just the ZCU111-PYNQ. Also I did not clone that repo into /PYNQ/boards so I’ve been using BOARDDIR and not BOARDS.

I’ve managed to get further with and HDMI evaluation license and this morning found it failed while working on the logictools for the Z1. I’ll try your suggestion with boards after moving the repo for the ZCU111

Writing bitstream ./logictools_wrapper.bit…
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Common 17-83] Releasing license: Implementation
243 Infos, 145 Warnings, 6 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:33 ; elapsed = 00:00:17 . Memory (MB): peak = 4136.016 ; gain = 0.000 ; free physical = 3788 ; free virtual = 16630
INFO: [Common 17-206] Exiting Vivado at Thu Oct 8 01:24:46 2020…
[Thu Oct 8 01:24:47 2020] impl_1 finished
wait_on_run: Time (s): cpu = 00:55:32 ; elapsed = 00:19:14 . Memory (MB): peak = 3901.129 ; gain = 0.000 ; free physical = 5901 ; free virtual = 18743
INFO: [Vivado 12-4895] Creating Hardware Platform: ./logictools.xsa …
CRITICAL WARNING: [Project 1-655] Project does not have Board Part set. Board related data may be missing or incomplete in the generated Hardware Platform.
WARNING: [Project 1-646] Board name, vendor and part not set in Hardware Platform.
WARNING: [Project 1-645] Board images not set in Hardware Platform.
INFO: [Hsi 55-2053] elapsed time for repository (/media/parallels/tools/Xilinx/Vivado/2020.1/data/embeddedsw) loading 0 seconds
INFO: [Project 1-1042] Successfully generated hpfm file
write_project_tcl: Time (s): cpu = 00:04:16 ; elapsed = 00:01:24 . Memory (MB): peak = 3901.129 ; gain = 0.000 ; free physical = 5643 ; free virtual = 18691
ERROR: [Common 17-141] Failed to write file content of prj/sources_1/bd/logictools/ip/logictools_mb_bram_ctrl_2/logictools_mb_bram_ctrl_2.dcp in zip archive.
INFO: [Common 17-206] Exiting Vivado at Thu Oct 8 01:26:17 2020…
Abnormal program termination (11)
Please check ‘/home/parallels/2020.1/PYNQ/sdbuild/build/PYNQ/boards/Pynq-Z1/logictools/hs_err_pid23533.log’ for details
segfault in /media/parallels/tools/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/vivado -exec vivado -mode batch -source build_bitstream.tcl -notrace, exiting…
makefile:16: recipe for target ‘bitstream’ failed
make[1]: *** [bitstream] Error 139
make[1]: Leaving directory ‘/home/parallels/2020.1/PYNQ/sdbuild/build/PYNQ/boards/Pynq-Z1/logictools’