CacheMetadataError ZCU102 PYNQ3.0.1 Vivado2022.1

Support
1

design_1.hwh (308.4 KB)
design_1.tcl (53.8 KB)
how to sollve this problem？Error message below:

CacheMetadataError  
...
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:452, in HwhFrontend._resolve_subordinate_addressing(self)
    450 for i in self._root.iter("MEMRANGE"):
    451     if i.get("MEMTYPE") == "REGISTER" or i.get("MEMTYPE") == "MEMORY":
--> 452         core = self.blocks[i.get("INSTANCE")]
    453         port = core.ports[i.get("SLAVEBUSINTERFACE")]
    454         if isinstance(port, SubordinatePort):

KeyError: 'axil_m'
2

I am trying to read data from PS with Datamover. I encountered this problem when loading the bit stream.

3

In this link (https://discussion.PYNQ.io/t/impossible-to-add-an-axi4lite-output-port-in-the-block-design-pynq/7965/3), block design does not support AXI or AXIL as the external interface of module design, so I’m going to give it a try.