I am working with “xczu47dr” and i face with “CacheMetadataError” when i import my bit file. the bit file is work in hardware by the way. I am new in PYNQ and I cant understand this error. I attached .hwh file. I appreciate any help.

block_design.hwh (1.4 MB)

Hi @Roghy,

Welcome to the PYNQ community.

It would be good if you can provide which version of the tool and which board you are using. Also, when exactly are you getting this error? Please, provide a code snippet

Hi, thanks for your answer.

I am using vivado 2021.1, xczu47dr-fsvg1517-2-e (active) , pynq 3.0.1
I get this error when i import the bit file.
Thank you very much.
CacheMetadataError.pdf (1.7 MB)


The error seems related to the DDR4. Can you please provide your block diagram from Vivado IP Integrator?


hopefully this two attached file be useful to help me.

Best regards

block_design.tcl (125.3 KB)

Sorry, the resolution prevents from checking anything. Are you able to export the design from IPI to PDF directly?

I am so sorry,
I should mention, I delete the DDR4 and now i can import bit file,
But it would be very nice to now what is wrong with DDR4 which I cant import the last bit file. The PYNQ is new for me, a little bit confusing.

block_design.pdf (315.7 KB)

Hi @Roghy,

Looking at your block design, I see that you are connecting the DDR4 controller directly to the M_AXI_HPM ports.

Typically the PL DRAM will not be connected to the PS. Can you elaborate a bit more what you are trying to accomplish?

One workaround you can try, although this may cause other issues, is to comment out lines 464-467 of this file /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/fronte nds/


hello, thanks for your prompt answer.
as I realized, I should use MMIO and DMA for this connection, is that right?
also, how can i access to /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/fronte nds/ from my jupyter to make change?

Thank you very much for your time and consideration.

Hi @Roghy,

as I realized, I should use MMIO and DMA for this connection, is that right?

This really depends on your application, but you probably may want a DMA to free the CPU of all this data movement. You can check this design to see how the PLDRAM is being used: GitHub - Xilinx/RFSoC-MTS: A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).

how can i access to /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/fronte nds/ from my jupyter to make change?

vim or nano via the command line in JupyterLab.


Hi @Roghy,

I have a branch up with a fix for the issue you’re facing (based on what @marioruiz was suggesting). Would you mind testing it, and if it solves your issue we can work on including it into the next release. In a terminal in JupyterLab could you try running the following:

python3 -m pip uninstall pynqmetadata
python3 -m pip cache purge
python3 -m pip install git+

And report back if that allows you to load the overlay?

Thanks so much,