Can not load bitstream to a custom board (pynq 3.0)

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1

<Custom board ultrascale+, pynq 3.0>
I have generated an image from xsa for my custom board. The image is generated but I am facing two problems here. First, the ethernet could not be found. So, I am trying to run my python script from the command line where the second problem comes with following error:

Traceback (most recent call last):
  File "/home/xilinx/jupyter_notebooks/q.py", line 22, in <module>
    overlay = Overlay('b.bit', ignore_version= True)
  File "/usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/overlay.py", line 348, in __init__
    self.download()
  File "/usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/overlay.py", line 424, in download
    Clocks.set_pl_clk(i, div0, div1)
  File "/usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/ps.py", line 303, in set_pl_clk
    cls._instance.set_pl_clk(clk_idx, div0, div1, clk_mhz)
  File "/usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/ps.py", line 311, in _instance
    cls._real_instance = _ClocksUltrascale()
  File "/usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/ps.py", line 463, in __init__
    self._crf_mmio = MMIO(self.CRF_APB_ADDRESS, 0x100)
  File "/usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/mmio.py", line 73, in __init__
    self.array = self.device.mmap(base_addr, length)
  File "/usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/embedded_device.py", line 581, in mmap
    raise EnvironmentError("Root permissions required.")
OSError: Root permissions required.

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
  File "/home/xilinx/jupyter_notebooks/q.py", line 24, in <module>
    overlay = Overlay('b.bit', ignore_version= True)
  File "/usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/overlay.py", line 348, in __init__
    self.download()
  File "/usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/overlay.py", line 424, in download
    Clocks.set_pl_clk(i, div0, div1)
  File "/usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/ps.py", line 303, in set_pl_clk
    cls._instance.set_pl_clk(clk_idx, div0, div1, clk_mhz)
  File "/usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/ps.py", line 311, in _instance
    cls._real_instance = _ClocksUltrascale()
  File "/usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/ps.py", line 463, in __init__
    self._crf_mmio = MMIO(self.CRF_APB_ADDRESS, 0x100)
  File "/usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/mmio.py", line 73, in __init__
    self.array = self.device.mmap(base_addr, length)
  File "/usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/embedded_device.py", line 581, in mmap
    raise EnvironmentError("Root permissions required.")
OSError: Root permissions required.

If run with sudo, the following error shows:

Traceback (most recent call last):
  File "/home/xilinx/jupyter_notebooks/q.py", line 2, in <module>
    from pynq import Overlay, allocate
ModuleNotFoundError: No module named 'pynq'

Any support would be much appreciated.

N.B.: I already have sourced the pynq_venv.

Regards,
Mizan

1 Like
2

Hi @mizan,

On the first problem, since it’s a custom board, I can’t give too much insight, but to look at changes we’ve made to other pynq boards when upgrading from v2.7 to v3.0 (especially in device tree and bsp configs).

If pynq isn’t found it typically means that whatever is trying to import pynq isn’t in the venv. Is it possible your script is opening another session/calling another script that’s importing pynq? Also just to clarify did you run sudo, then re-source pynq_venv? e.g.

sudo -i
source /etc/profile.d/pynq_venv.sh

Thanks
Shawn

1 Like
3

Thanks Shawn.

It just hangs when i run the script.

4

Just to clarify – it hangs when you run your “q.py” script? If that’s the case something in the code might be probing a memory register it shouldn’t be probing. Does the .hwh file definitely match the .bit file? Hangs are hard to debug, would try to go line by line until you find the call that causes the crash and hopefully that’ll give some more insight as to what’s going on.

Thanks
Shawn

5

Hi Shawn,
hwh file matches with bit file.
It stops even with the following the code:
from pynq import Overlay
ol=Overlay(“q.bit”)
gpio_v=ol.axi_gpio_0
^^^^It loads up to this.

Sorry i have not written where it hangs: whenever there is axi memory access, like
gpio_v.write(0x00,0x01)

6

Does every IP in the design crash when you try to read/write to it? Would double check if registers from ip_dict match what you expect from Vivado. Would also check if clocks are configured correctly, maybe it’s a wrong constraint setting? If I was more of a hardware guy I’d say drop in an ILA to inspect what the actual signals look like.

Thanks
Shawn

7

Hi Shawn,
I have not checked all the IPs, but I’ll do it. FYI, When I even click to autofill the line of a code e.g. after ol.pmod. then click tab to finish the line in the python editor it hangs there as well and i needed to restart the board. pmod here is a hierarchy. It works okay if it is not related to pynq.

edit: I tested the system with just two gpio ips and a hierarchy. It stops when I want to access the hierarchy.

8

Hi Shawn,
I messed up big time. I was trying to run pynq in two different procedures. One is petalinux with pynq overlay and another with pynq sdbuild procedure.
I mixed up both in this topic. My apologies.

Pynq sdbuild flow, it stops when trying to load bitstream with “sudo -i / source pynq_venv…”. It hangs there. Never goes forward.

These previous steps I have stated come in petalinux flow only.

9

Update: It also hangs with axi_iic ip,
when i try just this : IIC1= overlay.axi_iic_0

10

So far I have found two problems. It is not about hierarchy. When an interrupt line is connected to any IP or hierarchy, initializing that IP or accessing that hierarchy (e.g.: IIC1= overlay.axi_iic_0 or IIC1=overlay.pmod.axi_iic_0) results in a hang of the system. Second, if the IP is not connected to interrupt, it could be initialized but writing memory access also leads to hanging the system (e.g.: gpio.write(0x00,0x04).
Would be nice, if you have something to share for resolving this issue.

11

Typically a hang results from the PS initiating an axi transaction and getting no response from the fabric. As far as I know most common reasons for this that we see is the register address being written to/read from is wrong or there is no valid clock clocking the IP, something is wrong with the clock configuration. Hangs are tough to debug, so I don’t have a solution handy I’m afraid…

Is it the same axi clock going to the interrupt controller and other IPs? Could you validate that your clocks are actually running? Maybe some IP is stuck in a reset state, and that reset needs to be de-asserted.

Thanks
Shawn

12

The clock is coming directly from PL and i have tested the pl part of my project with this clock. It is working fine. Like I have tpg with atg and dvi output, which has been working fine with the same clock source. I can understand from your point that this is completely related to wrong memory access somehow with axi lite interface which is trying to access a different address than what is in the actual system.

I also have tried with smaller projects rather than going through my project, but unfortunately the same result.

13

Hi @mizan,

As Shawn hinted, you may need to add an ILA into the GP port of your design and observe what happens when you try to access the memory mapped region of the IP.

Have you tried to download and run your overlay using the Vitis flow? At least something simple, like an register read/write.

Mario