Is it possible to change the order that the DMA will go through allocated memory? As of right now, the DMA
controller will send a complete row from allocated memory then send the next row, and so on… can I change this order and how?
What are you trying to do?
The PYNQ DMA driver supports simple mode for this DMA:
https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf
The PYNQ allocate() allocates contiguous memory which is simpler and more efficient for the PL.
You could use a different DMA, and try to strided access (if this is what you want?). You would need to write your own Python code to drive this, which shouldn’t be very difficult to do.
Virtual memory on the PS might be difficult to deal with if you are trying to use scatter gather. I’m not sure if you can (easily) get the physical address(es) for a non-contiguous buffer.
Cathal
Sorry for the late response, I haven’t checked in a bit. So this strided access is certainly what I was interested in doing at the time. I will take a look at this documentation and see what I can do. Thank you!