Good afternoon,
I have created a simple counter VHDL block, from 0 to 15 bits. I would like to save this 16 bits in a csv file. Therefore, I want to use UART IP from xilinx in order to send this data to the PC.
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I currently have this diagram block. Where should I connect my personal block (counter_v1_0) outout (test_out[15…0]) in order to transmit this values to PC via UART.
The easiest way to do this would be to connect your counter output to a register that can be read from the PS.
For example, if you use PS GPIO or an AXI GPIO controller, connect the output of your counter to the GPIO (input). You could then use the PYNQ GPIO class, or the PYNQ MMIO class to read the value of the counter in Python. From there you could format to a CSV or whatever you want.
I made a some tutorials, some with videos. You can find a list here:
https://github.com/cathalmccabe/PYNQ_tutorials
These two may be most relevant.
You could also design your counter to have an AXI interface to allow you to read the register. If you are a beginner, this is a little more advanced as you need to understand the AXI interface. You would not usually write the code for this interface yourself. There is a tool in Vivado to write an AXI template for you that you can reuse for your design, but try the GPIO method first.
If you wanted to stream values from a counter; i.e. read a stream of 16 bit values from your counter then you would need some type of DMA to transfer the data back to PS memory. There are some DMA tutorials in the link about, and one that shows you how to do this from HLS without a separate DMA, but again these are more advanced.
Cathal
Thank you for your help.
Where can I find axi_gpio.bit file?
Marc
This design:
This is for Zynq Ultrascale+ (Kria KV260) so this bit file woudl not work with your board. You have a PYNQ-Z2 (Zynq) board. You would just need to add the additional Timer, and AXI GPIO IP to your Vivado design that you posted a screenshot above. This should only take a few minutes to build.
Cathal
Hello,
I am currently havin issues with .hwm files. The first time the project is compiled hwh file is generated correctly. Nevertheless, when I generate output products, then a synthesis, implement and bitstream, the hwh file is still the same and it has not been updated. Indeed, even if i reset output products the file is still the same.
Any idea?
Thank you
The file you need is the .HWH file (not .hwm). Depending on the project changes, they may not impact this file.
Did you try generate a bitstream and use the HWH file with this to load your overlay?
Regards,
Cathal
I found the .hwh files in the.xsa folder.
I currently have a new issue. The data I have to read through AXI GPIO is too fast and I miss a lot of words of bits. These word of bits are ready by Python code with PYNQ Overlays. How should I solve this issue?
Check the part in my original reply
https://discuss.pynq.io/t/tutorial-pynq-dma-part-1-hardware-design/3133
Streaming would allow you to keep up with the data and transfer a number of samples. You can transfer a block of data at a time (limited to 8MB).
You need to connect your data source to the AXI stream interface of the DMA. You really need to have VALID and READY handshaking signals to do this. Do you understand the AXI stream interface protocol? If not, you many need to learn about this.
Cathal
Is it as simple as to create a custom IP with AXI via VIVADO?
