We need to capture raw samples from both ADCs simultaneously at 512MHz to the PLDDR4. On the ZCU111 this wasn’t an issue: the default PL DDR4 clock is 300MHz so the data-rates work out. On the RFSOC 2x2 the PL DDR4 clock defaults to 200MHz so this isn’t possible.
Page 11 of https://www.rfsoc-pynq.io/pdf/RFSoC_2x2_UG.pdf has a rather scary note about one shot reprogramming of the clocks (for that matter it isn’t clear if that one-shot was used at the factory.
Has anyone given thought to the specific steps involved? I’m a bit worried about bricking out boards or running into other gotchas with the board presets in Vivado.