Changing reference clock rate of RFDC in RFSoC 4x2 would crash pynq system

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1

Dear all,

I am using the RFSoC 4x2 with pynq 3.0.1.
The FPGA firmware is the base one from:

From the base Vivado project, I tried to make some change to re-make bitstream.
If I changed the sampling rate and reference clock like:

  • Default: 4.9152 Gsps, 491.52 MHz
  • New: 3.6864 Gsps, 204.8 MHz
    All I did was opening the RFDC IP, changed them, re-compiled.

With the new bitstream, I was following this notebook:

In step 1, the bitstream is updated to the new one
In step 2, I specified the lock rate: base.init_rf_clks(lmx_freq=204.8)
xrfclk has the txt file for 204.8 MHz, so it is no problem.
However, in step 9, while setting up base.radio.transmitter.channel[i].control.gain, pynq always crashed with connection loss.

For this problem, I did some more tests.
If the reference clock is 491.52 MHz as default, changing the sampling rate is no problem.
But once the reference clock is changed to other rate, the same problem would always happen.

I believe that BaseOverlay allows any kind of proper update/change from the base Vivado project for user’s convenience if the basic structure of PS remain the same.
In such a case, if reference clock is different, if there any other changes which are required in Vivado elsewhere or in the pynq notebook?

Thank you in advance.

2

I just did some more checks on this problem,
The supported clock rate for lmx2594 includes (MHz):
102.4, 204.8, 409.6, 491.52, 737.0.
No matter how the RFDC config is changed in Vivado project, if the default 491.52 MHz is assigned by the init_rf_clks function:
base.init_rf_clks(lmx_freq=492.52)
Pynq is working correctly.

However, if the other clock rate is assigned by init_rf_clks:
base.init_rf_clks(lmx_freq=204.8)
base.init_rf_clks(lmx_freq=409.6)
…
Pynq must be crashed if I access the transmitter or receiver.
I guess there is something missing in the procedure if one would like to change the lmx clock rate for RFDC.