I have designed an overlay and can set variables and call the top function and everything is working fine. I synthesized using ap_ctrl_none. When synthesizing using ap_ctrl_hs instead of ap_ctrl_none one get one input and three outputs, which is what I want. But the question is whether there is a way to write to ap_start and read ap_idle, ap_done and ap_ready through my overlay?
After synthesizing, I don’t get addresses for these control io’s in my *_hw.h file, I only get addresses for my variables.
How to control the ap_ctrl_hs through overlay?
Edit: The one approach I’m considering is to design another block using ap_ctrl_none, and have it interfacing the ap_ctrl_hs block.
You may be better posting HLS question on Xilinx forums
It is possible to connect GPIO to write signals, and you could poll to read a signal, but this probably isn’t what you want to do.
I’d recommend you add the following to put the control interface on an AXI lite Slave:
#pragma HLS INTERFACE s_axilite port=return
You can control this from PYNQ with MMIO read()/write()
Ref:
https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/managing_interface_synthesis.html
Cathal
Thank you for your reply.
Funny, I’ve read exactly the page you are referring to. And it’s actually where I found ap_ctrl_hs and its usefulness. I was wondering about how to control this, ap_ctrl_hs, through Pynq Overlays.
But anyway, thanks for the tip. I’ll post a reply when I’ve managed to go through all my trial-and-errors.
Maybe (again) I’m an idiot… It just might be this simple.
