This isn’t supported directly. i.e. the PYNQ APIs for the DMA class don’t support this.
However, you can use PYNQ to read/write the DMA control registers, so I think you should be able to set the cyclic bit “manually” or modify the PYNQ API.
Have a look at this tutorial for the DMA, and in particular look at part 2 (linked from part 1) and the register map:
https://discuss.pynq.io/t/tutorial-pynq-dma-part-1-hardware-design/3133
You need a few changes. You need to enable Scatter Gather, you need to connect to the SG ports. You need to make sure your memory buffer(s) are contiguous - i.e. use PYNQ allocate() to create them.
This is the start function. You can see it is a simple MMIO write to the control register https://github.com/Xilinx/PYNQ/blob/master/pynq/lib/dma.py#L323
Note that this is for the _SGDMAChannel
It either writes 0x1001 or 0x1 depending on if you want interrupt enabled.
You would either need to manually do an MMIO write() to the control register and include the cyclic bit (bit 4, so you would write 0x1011 or 0x11), or you could modify the start() method.
Cathal