Receive Cyclic DMA

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1

Hi,
I need to continously write ADC samples (AXI-stream) to DDR through DMA on a single buffer overwriting old data until a PL module detects a trigger condition and decides to end the DMA transfer. The PL module is also responsible of tracking last data position in receive buffer.
From other posts it seems Pynq does not support Cyclic DMA on receive, even on 3.0 version like mine.
Is there any workaround? Should I use Axi_Datamover IP?

PYNQ version is 3.0.1
Board name is RedPitaya 7020
Tool Version is Vivado 2024.1

Thanks in advance!

2

I managed the cyclic DMA writing/reading the AXI-DMA registers and the Block Descriptors (BD). I made a 2 BDs chain. According to PG021 I programmed the _TAILDESC register to an intentionally wrong value but, differently from example given in PG021, I obtained the cyclic behavior only when I programmed a value beyond the last BD.
Hope it helps…

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