PYNQ: PYTHON PRODUCTIVITY FOR ZYNQ

FIFO using PYNQ DMA

I am trying to understand how to use DMA on PYNQ, and I create an FIFO example by following the article, Using the AXI DMA in Vivado.
I am trying to run this design on PYNQ Python API.

My block design is shown as following picture

However, the values of output array buffer is stile all zero, after I call “dma.recvchannel.transfer(output_buffer)”.
And if I call sendchannel.wait() and recvchannel.wait(), the system is stuck.
So, my question is how to using DMA in this FIFO Example?

Here is my code,

Can you first try the design without the axi interrupt block? I would say start with the DMA without any interrupt output, then if it is working, connect the interrupt directly to the PS interrupt input.

In addition to Rock’s suggestion, the PYNQ AXI DMA class doesn’t currently support scatter gather. It looks like you have enabled this on your DMA IP. Can you try disable this?
If it still isn’t working, can you post your DMA configuration settings?

Cathal

Thank you for answering!!
I have remove the AXI Interrupt block and disable the Scatter Gather. The DMA configuration is as following

.
And the Block Design
.

The problem now is, I can successfully download the bitstream file

ol = Overlay('/home/xilinx/jupyter_notebooks/JiaMing/DMA_lab1/FIFO/dma_fifo.bit')

, but the whole system is busy and stuck when I create the DMA object by

import pynq.lib.dma
dma_fifo = ol.axi_dma_0

Is there any suggestion? Thank you.

Which board and which version of PYNQ are you using?

Can you post all your code?
Are you sure you updated the Tcl/HWH and copied both to the board/removed the old files?
Did you power cycle your board (turn off, and on again)

I would also advise you set the “Width of Buffer length register” to the maximum 26.
2^14 is 16384, the max size number of bytes data you can currently transfer.

Cathal

I abandon the original project since it occasionally happens to “synthesis and implementation out-of-date” error. Then I created a new project from the .tcl file from previous project.
Now my application works normally!!

To summarize this work with modifications from above suggestions:

  1. I mainly follow " Using the AXI DMA in Vivado" to create the Block Diagram.
  2. remove the interrupt module
  3. disable DMA scatter-gather
  4. set the “Width of Buffer length register” to maximum 26.

Then the Python code


Thanks for your helps!