Sorry, I missed your reply.
EDIT: I’m looking at the image of the block diagram. How do you have the AXI stream output connected? (It is hard to see in the image.) Are you managing the AXI Stream VALID/READY signals?
Can you try readback the control register and the status registers from the register_map to check if the DMA is running/idle/error etc. and if the cyclic bit is set correctly?
Info to do that here:
https://discuss.pynq.io/t/tutorial-pynq-dma-part-2-using-the-dma-from-pynq/3134?u=cathalmccabe
Cathal