I just took that code as an example and I modified it according to my algorithm specifications in the HLS.
I have changed to int32 and it starts printing 4096, but it still keeps running without showing any result.
Thanks for your reply. I am able to run the example one on different boards but not on PYNQ Z2.
I am using a ZCU111 board and it has a Zynq Ultrascale +. I modified the DMA parameters but still the result doesn’t show up.
The ZYNQ U+ burst length and AW user and AD user data width is not matching with my DMA. it shows warnings
It looks like you have a mismatch in the data widths of your DMA/IP. I see 128 (DMA MM data width) /64/32/16 (streams) at different places in your design.
What are your data widths in your design?
Try to match the data widths of the DMA MM ports to the Zynq interfaces. They DMA can remap your data width to the width of your stream, but you should think about the number of data transfers.
Did you try add an ILA like I suggested earlier?
You could also try replace the Smart Interconnect with a AXI interconnect. Sometimes there can be issues with Smart Connect.
I think you need to step by step ensure each part:
Separate part A)
1st HLS tlast syntax is added and did you tried the I/O sanity of the main.cpp to check all layers are normal?
2nd Any violations when the HLS is completed?
Separate part B)
1st do a simple dummy data test on the DMA by replacing the HLS just a simple fifo feedforward (Did this success or not)
2nd replace the fifo to HLS block and check this is normal or not
If the basic fifo cannot grep all data you don’t need to consider time on the HLS block as the basic communication blocks are not sure yet.