Dear all I write a simple memory read and write code in verilog and also put a tlast signal when reading memory of my Ip completed as mention in PYNQ DMA section.
But when I write code of python ad pass a array into input buffer it works fine. but hardware didn’t send back my data at output buffer.
its kind of infinite wait loop.
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Can you specify a bit more about your problem/setup?
functions called in python, data line name at output buffer etc.
Yes sure I can Try with more clear words.
I write a memory read and write Verilog code in Vivado for ultra96V2 board code is attached. memcodev.txt (2.0 KB)
Then I make proper Hardware using Zynq processor and DMA and my custom IP. Diagram is also attached.
So I write a python code using PYNQ just to check memory loopback (mean I will store a simple row of an image write it into virtual buffers of PYNQ Overlay it will send it to my custom IP (Core) using DMA controller. my IP (core) simply store image row and send back to DMA controller to PS.
Error is : I Don’t received data Back in my output Virtual buffer . it seems it kind of stuck in waiting loop. there might be a handshaking problems in between PL to PS. I am using Tready, Tvalid, T Data and Tlast signals for master slave hand shaking.
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Hi,
I look your code at a glance, you are missing the keep signal. I don’t know if the DMA is configured to use or not.
Did you write a testbench for your code?
Mario
According to
T keep signal is absent only valid signal is required. if I am wrong please enlighten me to solve this problem Thanks
That depends on how the DMA is configured. Please share those details
You need the keep signal, the DMA uses it and there is not configuration field to remove it.
What is the DATA_WIDTH in your core? If this is still 8, you also need to change the Stream Data Width
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It may also be useful to print the register information for the DMA:
dma.register_map
This should give more info about the status of the DMA.
Cathal
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