DMA for xc70z030fbg676-1 not working!

Support
1

HI all,

I have tried DMA example for PYNQ Z2 board, and it is working !!!

Test setup

  1. We are trying the same example with the custom board ( xc70z030fbg676-1) SOC.
    2)Pynq version - 2.6.0
  2. VIvado -2020.1
    4)Vitis 2020.1
  3. Petta Linux-2020.1

Problem Statement

  1. I’am able to send the data through DMA and the status register says 400bytes are transfered.
    2)When i try to read back the same data through DMA Error pops up saying DMA channel not started.

Example design Link :
https://pynq.readthedocs.io/en/v2.4/pynq_libraries/dma.html

design_1.pdf (118.1 KB)
pynq_dma_error (1)

2

I don’t see a DMA in the block diagram for the design you posted (pdf).

The image is too small to read the code. Could you please repost a larger image or the error message that you see?

Cathal

1 Like
3

Hi Cathal,

I have attached a block diagram with DMA and also cropped the error message.Please find the attachment.

Regards
Akarsh
ps.pdf (80.3 KB)

pynq_dma_error (1)
pynq_dma_error (1)1920×1080 192 KB

4

Would you be able to provide the output of dma_fifo.register_map?

Peter

5

Hello Peter,

I please find the register map

RegisterMap { MM2S_DMACR = Register(RS=0, Reset=0, Keyhole=0, Cyclic_BD_Enable=0, IOC_IrqEn=0, Dly_IrqEn=0, Err_IrqEn=0, IRQThreshold=1, IRQDelay=0), MM2S_DMASR = Register(Halted=1, Idle=0, SGIncld=0, DMAIntErr=0, DMASlvErr=0, DMADecErr=1, SGIntErr=0, SGSlvErr=0, SGDecErr=0, IOC_Irq=1, Dly_Irq=0, Err_Irq=1, IRQThresholdSts=0, IRQDelaySts=0), MM2S_CURDESC = Register(Current_Descriptor_Pointer=0), MM2S_CURDESC_MSB = Register(Current_Descriptor_Pointer=0), MM2S_TAILDESC = Register(Tail_Descriptor_Pointer=0), MM2S_TAILDESC_MSB = Register(Tail_Descriptor_Pointer=0), MM2S_SA = Register(Source_Address=939810816), MM2S_SA_MSB = Register(Source_Address=0), MM2S_LENGTH = Register(Length=400), SG_CTL = Register(SG_CACHE=0, SG_USER=0), S2MM_DMACR = Register(RS=0, Reset=0, Keyhole=0, Cyclic_BD_Enable=0, IOC_IrqEn=0, Dly_IrqEn=0, Err_IrqEn=0, IRQThreshold=1, IRQDelay=0), S2MM_DMASR = Register(Halted=1, Idle=0, SGIncld=0, DMAIntErr=0, DMASlvErr=0, DMADecErr=0, SGIntErr=0, SGSlvErr=0, SGDecErr=0, IOC_Irq=1, Dly_Irq=0, Err_Irq=0, IRQThresholdSts=0, IRQDelaySts=0), S2MM_CURDESC = Register(Current_Descriptor_Pointer=0), S2MM_CURDESC_MSB = Register(Current_Descriptor_Pointer=0), S2MM_TAILDESC = Register(Tail_Descriptor_Pointer=0), S2MM_TAILDESC_MSB = Register(Tail_Descriptor_Pointer=0), S2MM_DA = Register(Destination_Address=0), S2MM_DA_MSB = Register(Destination_Address=0), S2MM_LENGTH = Register(Length=0) }

Regards
Akarsh

6

Hi Peter

Please find the register map

RegisterMap {
  MM2S_DMACR = Register(RS=0, Reset=0, Keyhole=0, Cyclic_BD_Enable=0, IOC_IrqEn=0, Dly_IrqEn=0, Err_IrqEn=0, IRQThreshold=1, IRQDelay=0),
  MM2S_DMASR = Register(Halted=1, Idle=0, SGIncld=0, DMAIntErr=0, DMASlvErr=0, DMADecErr=1, SGIntErr=0, SGSlvErr=0, SGDecErr=0, IOC_Irq=1, Dly_Irq=0, Err_Irq=1, IRQThresholdSts=0, IRQDelaySts=0),
  MM2S_CURDESC = Register(Current_Descriptor_Pointer=0),
  MM2S_CURDESC_MSB = Register(Current_Descriptor_Pointer=0),
  MM2S_TAILDESC = Register(Tail_Descriptor_Pointer=0),
  MM2S_TAILDESC_MSB = Register(Tail_Descriptor_Pointer=0),
  MM2S_SA = Register(Source_Address=939810816),
  MM2S_SA_MSB = Register(Source_Address=0),
  MM2S_LENGTH = Register(Length=400),
  SG_CTL = Register(SG_CACHE=0, SG_USER=0),
  S2MM_DMACR = Register(RS=0, Reset=0, Keyhole=0, Cyclic_BD_Enable=0, IOC_IrqEn=0, Dly_IrqEn=0, Err_IrqEn=0, IRQThreshold=1, IRQDelay=0),
  S2MM_DMASR = Register(Halted=1, Idle=0, SGIncld=0, DMAIntErr=0, DMASlvErr=0, DMADecErr=0, SGIntErr=0, SGSlvErr=0, SGDecErr=0, IOC_Irq=1, Dly_Irq=0, Err_Irq=0, IRQThresholdSts=0, IRQDelaySts=0),
  S2MM_CURDESC = Register(Current_Descriptor_Pointer=0),
  S2MM_CURDESC_MSB = Register(Current_Descriptor_Pointer=0),
  S2MM_TAILDESC = Register(Tail_Descriptor_Pointer=0),
  S2MM_TAILDESC_MSB = Register(Tail_Descriptor_Pointer=0),
  S2MM_DA = Register(Destination_Address=0),
  S2MM_DA_MSB = Register(Destination_Address=0),
  S2MM_LENGTH = Register(Length=0)
}



Regards 

Akarsh
1 Like
7

The send channel is showing a decode error - can you make sure that the PS’s DDR address space is correctly assigned for the DMA in the address editor in Vivado.

The receive channel isn’t showing any activity which is slightly weird. Hopefully the addressing is the problem for both

Peter

8

Hi Peter,

I have attached the Address space of DMA in vivado to this email.Please find the attachment.
Can you please suggest what changes need to be done?

Regards
AKarsh

address_spcae.png
address_spcae.png1920×1080 176 KB

Akarsh

1 Like
9

Your base addresses for the HP0_DDR_LOWOCM need to be 0 and have a range of 512 MB

Peter