DMA.recvchannel.wait() always hanging

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1

Hi guys! I am new for PYNQ and design my own IP via Vitis HLS. My board is ZCU104 and according PYNQ version.

But all my IPs using AXIS interface for output would hang on, typically stuck at dma.recvchannel.wait() forever. For this simple official example:

#include “ap_axi_sdata.h”
#include “hls_stream.h”
#define DWIDTH 32
#define type ap_int
typedef hls::axis<type, 0, 0, 0> pkt;
void example(hls::stream &A,
hls::stream &B)
{
#pragma HLS INTERFACE axis port=A
#pragma HLS INTERFACE axis port=B

pkt tmp;
pkt t1;
A.read(tmp);
t1.data = tmp.data + 5;
B.write(t1);

}
Part of host python code and error report show below:

24244bc31f991ec1bfeae8044b574db
24244bc31f991ec1bfeae8044b574db698×848 114 KB

I was suspecting that is because TLAST was not set correctly. So I revised the above C++ code:

#include “ap_axi_sdata.h”
#include “hls_stream.h”
#define DWIDTH 32
#define type ap_int
typedef hls::axis<type, 0, 0, 0> pkt;
void example(hls::stream &A,
hls::stream &B)
{
#pragma HLS INTERFACE axis port=A
#pragma HLS INTERFACE axis port=B
#pragma HLS INTERFACE mode=s_axilite port=return
pkt tmp;
pkt t1;
A.read(tmp);
t1.data = tmp.data + 5;
t1.last = 1;
B.write(t1);
}

And also I tried that pass the TLAST from input signal to outputs. But the error still happens. BTW the DMA IP is set as the tutorial with max Width of Buffer Length Register(26).

eed08f0d0aeba63ae1f232ff689d0e6
eed08f0d0aeba63ae1f232ff689d0e61262×475 40 KB

I’ve been struggling for this a few days. Any suggestions would be appreciated.

1 Like
2

A couple of things here:
In which version you have used to generate this IP? I believe it should not generate the IP at all as you have used two completely different typedef for port mapping and reading the data in main body. Now, I suppose somehow in your case, it is generated, then you should check the port mapping in hls report. You should verify all the ports have your desired length. Also, it would be best if you defined t1.keep bits to all set.
Another thing, I have noticed is that you have axi lite port for controlling your IP but you have not started the IP in your Python code.

1 Like
3

hello,
Did you sovle your problem? Can you give me some information? I have the same problem as you.
thank you very much.

1 Like