DMA sends and receives multiple times

[j_pynq]

Hi,
I was following Tutorial: using a HLS stream IP with DMA (Part 1: HLS design)

My source code is based on https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/blob/2021.2/Interface/Streaming/using_axi_stream_with_side_channel_data/example.cpp

#include "ap_axi_sdata.h"
#include "hls_stream.h"


void example(hls::stream< ap_axis<32,2,5,6> > &A,
	     hls::stream< ap_axis<32,2,5,6> > &B)
{
#pragma HLS INTERFACE axis port=A
#pragma HLS INTERFACE axis port=B
#pragma hls interface s_axilite port=return

	ap_axis<32,2,5,6> tmp;
    while(1)
    {
	A.read(tmp);
	tmp.data = tmp.data.to_int() + 5;
	B.write(tmp);
     if(tmp.last)
     {
         break;
     }
    }
    

}

You can also see the TLAST signal had been sythesised