Multiple DMA wait() problem

Support
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PYNQ v2.4 Ultra96v2, Vivado 2023.2 and Vitis HLS 2023.2
Hi, I created an IP core with AXI stream interface successfully (I can see all interface signals). After creating the design with Vivado 2023.2 I can’t transfer via DMA, in particular my code doesn’t pass wait(). I attach the HLS code. Thank you for your help.

image
image1728×651 131 KB

xf_stereolbm_accel2.cpp (3.7 KB)

2

Hi,
Did you check this post?

Debugging Common DMA Issues [Part 3]

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I did. I have 3 DMAs in my design and I can’t find anything that can help

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