I am trying to build PYNQv2.4 image on other zynq7020 board with base vivado project that includes AXI SPI ip( PS use spidev driver to read/write by emio).
I have successfully tested it on Petalinux，so I write extra kernel config to metapynq:
CONFIG_CMA_SIZE_MBYTES=256
CONFIG_SPI_XILINX=y
CONFIG_SPI_ZYNQ_QSPI=y
CONFIG_SPI_SPIDEV=y
system_dtb.txt (13.6 KB)
Spi devicetree is generated in system.dtb as before, but the linux occurs error：spidev spi0.1: SPI transfer timed out.
I also tired to use my previous successful petalinux project to adopt pynq, writed extra kernel config:
CONFIG_XILINX_APF=y
CONFIG_XILINX_DMA_APF=y
With xlnk device tree, it can run with pynq filesystem, using functions such as ‘import pynq’ , ‘pynq.Overlay(‘bit’)’ and spidev, but error occurs in Partial Reconfiguration：
/usr/local/lib/python3.6/dist-packages/pynq/pl_server/device.py in download(self, bitstream, parser)
578 fd.write(flag)
579 with open(self.BS_FPGA_MAN, ‘w’) as fd:
→ 580 fd.write(bitstream.binfile_name)
581
582 super().post_download(bitstream, parser)
TimeoutError: [Errno 110] Connection timed out
Any suggestion is appreciated.