Does PYNQ support floorplan masking (moved)

Do PYNQ support floor plan masking?
Really interested idea or I am getting this wrongly.
An overlay is reconfiguring the PL entirely?
Maybe unifying the design and control via AXI is easier?

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Sorry I dont have any idea about these method. If there is any support document then please share.

This is called DFX (Dynamic Function Excahnge) where you only program part of the Programmable logic, and can load different partial designs on demand. It is supported by Xilinx tools and PYNQ. This used to be called Partial Reconfiguration. It is recommended for advanced FPGA designers.
More info:



I am not sure how flexible can be achieve as what I know is there are GTX and BUFG BUFH and other consideration here.
BRAM as well mostly this is more important as well.
But real speaking when a 7020 default PYNQ board only got that little LE and DSP why bother on such idea of cause if extending the idea to a higher density FPGA that will be the case I guess.

Hi @briansune,

Cathal answer your question. PYNQ support DFX and it is something we use extensively in the composable overlay. GitHub - Xilinx/PYNQ_Composable_Pipeline: PYNQ Composabe Overlays
In the coposable video pipeline, you can see how we augment the functionality of the design by using DFX. Without DFX, we would have not been able to support all of these applications.

why bother on such idea

Whether it makes sense or not it is a decision for a savvy hardware designer to make, and well outside the scope of PYNQ and this forum.



I guess you missed the entire story and such moving comment to a new post topic. Well I didn’t open a post to ask this as it is belongs to the other post as comment. So I got no idea why it is moved. Meantime the original post is asking two overlay so simply fact is when it can be simplify why complicate things when the easiest design is not even achieve.

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This is what one of the modulator answer so the simple answer is no you can’t achieved runtime two sector reconfiguration control and overlay reloading.
This is what my original comment belongs to and stop splitting comment to new post to lost comment relationship.

Well I guess it is better I hand it back to those modulators to answer these question as this community is handling people more then topics.

When I never mention any make sense but targeting the question from top to bottom here.
Boycott people will not make the community better or encourage engineer to help out here.

Before I leave this post 1 16bit FFT with the best algorithm consume over 95% overall resources of 7010 ZYNQ FPGA so unless it is necessary to run-time reconfig thing like CNN training to inference design. Try not to do so. Meantime reconfiguration time is slow so try to utilize the Logic Element design and Process Unit idea on FPGA rather then reprogram. Meantime also, consider throughput with floorplan limitation sure introduce congestion and performance degradation. So when 100% of LE is split to 50/50 the overall LE to maintain max setup time pass is around 30% / 30% on two balance sectored floorplan.

Well I guess I will make mistake here, correct me if necessary.

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@briansune I split your comment into a separate question and answered it. I try to do this when people ask a new or different question on an existing post. I thought it might be a relevant separate question for other PYNQ users and that it would be valuable as a separate topic.
I also thought DFX might have been outside the scope of the original post.
I don’t always get this right so I apologise if you didn’t like the way I split the post or my answer to your question about DFX in this topic.

In response to your question I agree with you that if you have a large IP, it can consume most or all of the resources of a Zynq 7020 and DFX may not be of much value. Other designs can benefit from DFX on a 7020. Actually one use case for DFX is where you may be able to use a smaller device and time share functions instead of using a larger device.
In my opinion DFX is not a beginner topic which is why I didn’t suggest it (yet) on the other post.


I think what the original post question is indeed targeting such idea on DXF floor planning with multi sectors.
Time interleaving on overlay means you need memory stack to hold intermediate data so this resetting in a general sequential questions.
So you are suggestions a time interleave acceleration with run-time reconfig. Wonderful a good topic to research but not on the scope of this community but what I can see is you are doing a pseudo ASIC concept so even worst the topic get more even complex now. Consider a 3 stage interleave operations:

  1. fetch
  2. reload
  3. store
    How much time do such design can benefit actually (well, I should not judge)
    But action-wise (fetch + store + [reload - acceleration]) vs (fetch + store - [acceleration / #module]) now let this community to test out this.

So, should I consider there is no way to use two overlay at a time? because I don’t find any solution using DXF. If there is any then please help.

No, you cannot use two overlays at the same time. Each overlay occupies the full FPGA. To use a different overlay, you have to reconfigure the full FPGA. Hence, removing the previous overlay.