As the subject suggests, I’m looking for any and all texts describing the FPGA Reconfiguration Mechanism that is implemented by/for PYNQ.
- I’m completely new to PYNQ, with little experience in firmware design.
- I do have high(er)-level understandings of HDL and how Vivado stitches the various components together.
- Adding to that, some forms of understanding of Soft-core Processors implemented on FPGAs, e.g. MicroBlaze.
Aside from gaining clarity on the Reconfiguration Mechanism itself, I mainly want to figure out whether Partial Reconfiguration is implemented in some way for this process. Any feedback would be greatly appreciated; please and thank you!