Empty bitstream files


I am new to pynq and educating myself following tutorials on this web site. I tried tutorials creating overlays Adder and FIR_filter. In each case when I open the overlay in python and list the content of I do not see any IP s.
Like this:

Load the overlay

overlay = Overlay(’/home/xilinx/pynq/overlays/fir_accel/fir_accel.bit’)

list content

Default documentation for overlay /home/xilinx/pynq/overlays/fir_accel/fir_accel.bit. The following
attributes are available on this overlay:
IP Blocks

    filter               : pynq.overlay.DefaultHierarchy

Everything looked fine in Vivado .There were no error messages when generating the bitstream ( (there were few warnings which looked harmless) and reported that the bit-stream was generated successfully. But after uploading .bit and .tcl files to PYNC board and looked at them in Jupyter notebook, always see the same null result.

Any help resolving this issue greatly appreciated. I tried multiple times using Vivado 18.3 and 19.2, and have spent several days struggling find what is going wrong.Thanks.


The file is inside the vivado project directory:

You should change the hwh file name. And it must be in the same directory and with same name.
In this case: fir_accel.hwh


You meant copy fir_accel.hwh to directory

/home/xilinx/pynq/overlays/fir_accel ?

I just did that, but it did not fix it. Thanks.


Hi Lalith,

No, copy it to the same directory of fir_accel.bit

For example:

Hi Yao-Ming,

Yes that directory is the one with fir_accel.bit and fir_accel.tcl.

Anyway now it is working, problem seems to be with my license. Somehow vivado had failed to connect to the license server and picked up some default license which did not generate bitstream correctly.

Still when I type overlays? it does not list any IPs, which I do not understand why.

But it is functional.

I also found that it works without the fir_accel.hwh, perhaps for this particular example it is not needed.

Thank you for your help.


Hi Lalith,

I’m glad that you solved the problem!
It’s so strange, I haven’t had that issue using Vivado.


Tcl file will be soon be deprecated. We use hwh file as the overlay file, so you have to put .bit and .hwh in the same folder when you import your overlay.

Also, if you can attach the block design it would be easier for us to see why you can’t see the hierarchy. There are some rules - for example, the PS block has to stay at the top level, not to be wrapped inside a hierarchical block. That way, the python parser is able to extract the correct information.

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Block tcl and a screen shot of the design are attached.

fir_accel.tcl (46.7 KB)

The tcl looks fine to me. So there might be a bug for the tcl parsing. Since we are deprecating tcl file soon, I will not try to resolve it at this moment. Please use the hwh file, put it along to the same location as your bit file. In that way after you instantiate overlay object, you should be able to see something using overlay?.