PYNQ: PYTHON PRODUCTIVITY

Errors when generating a bitstream for the base overlay

I want to be able to use the HDMI out on the PYNQ_Z2 along with some IP that I created. I am trying to do this by rebuilding the base overlay with my IP included in the block design. However, when I try to generate the bitstream I get an error about Unconstrained Logical Ports. If I add the flag listed in the error to tcl.pre then the bitstream is generated without any issues. However, I am worried that this doesn’t fix the issue and I may end up breaking my board or my monitor.

If anyone knows how to fix this issue I would greatly appreciate the help.

Aditional information.
I am using version 2018.3 of the vivado tools to rebuild the base overlay.
My design is using the vivado IP found on git. I am using v2.4 since they were built with vivado 2018.3.


I have tried using the constrains file found in this git repo and the one found on the pynq read the docs.
https://pynq.readthedocs.io/en/v2.5/overlay_design_methodology/board_settings.html

My full error message is:
[DRC UCIO-1] Unconstrained Logical Port: 107 out of 251 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: codec_addr[1:0], sdata_o, sdata_i, lrclk, bclk, sws_2bits_tri_i[1:0], rpi_gpio_tri_io[19:0], pmodb_gpio_tri_io[7:0], pmoda_rpi_gpio_tri_io[7:0], hdmi_out_hpd[0], hdmi_out_data_p[2:0], hdmi_out_data_n[2:0], hdmi_out_clk_n, hdmi_out_clk_p, hdmi_in_ddc_scl_io… and (the first 15 of 34 listed).

You probably just missed the step to include the constraint file.
https://github.com/Xilinx/PYNQ/blob/master/boards/Pynq-Z2/base/vivado/constraints/base.xdc

Your problem is that your IO have not been given location constraints. i.e. you have not connected ports in your design to physical pins.

If you are not using them, this won’t matter for things like the switches (sws_2bits_tri_i) RPi header (rpi_gpio_tri_io), pmod headers (pmodb_gpio_tri_io[7:0], pmoda_rpi_gpio_tri_io).
For the HDMI pins (hdmi_out_hpd[0], hdmi_out_data_p[2:0], hdmi_out_data_n[2:0], hdmi_out_clk_n, hdmi_out_clk_p, hdmi_in_ddc_scl_io …), if they are not connected, your design won’t work.

Cathal

Hi Cathal, Thanks for the response.

I have tried doing this, but perhaps I am missing a step. Under my project sources, I have added base.xdc to the constraints folder. Next when I run the Autoplace I/O ports tool it is able to assign 237/251 ports. Are there some additional constrains I am missing?

Can you post the error and list of pins you are missing?
If the port names got modified (slighlty) for some reason from what is in the constraints file, then the constraint won’t be applied.

Once you have synthesized or implemented the design, if you can open the “IO planning view” in Vivado, it should be obvious in the GUI which pins are missing constraints.

Can you describe your build flow - the steps you are taking? If you are using a makefile/Tcl file, can you post it?

Cathal

When generating the the bitstream I am stilll getting the following error.
[DRC UCIO-1] Unconstrained Logical Port: 107 out of 251 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: codec_addr[1:0], sdata_o, sdata_i, lrclk, bclk, sws_2bits_tri_i[1:0], rpi_gpio_tri_io[19:0], pmodb_gpio_tri_io[7:0], pmoda_rpi_gpio_tri_io[7:0], hdmi_out_hpd[0], hdmi_out_data_n[2:0], hdmi_out_data_p[2:0], hdmi_out_clk_n, hdmi_out_clk_p, hdmi_in_ddc_scl_io… and (the first 15 of 34 listed).

Through the IO planning view I can see that some of the I/O ports are not assigned to a Package Pin.
Vaux1_53062, Vaux5_53062, Vaux6_53062, Vaux9_53062, Vaux13_53062, Vaux15_53062, and Vp_Vn_53062 are the unassigned pins. Should I assign these manually, and if so do they need to be assigned to specific pins.

For workflow, I started this project using build_base_ip.tcl and base.tcl from the repo found above. From there I added my IP to the block diagram and ran through the synthesis and implementation using the GUI. I have not been using makefiles or tcl.

It looks like the pins match what should be in the base.xdc, so it looks like something is going wrong and the constraints are not being applied.

Can you see the problem pins in the IO planning view?

You can copy the constraints from the .xdc and execute them as Tcl commands in the Vivado Tcl console for your project. It might be worth checking if you can do this.

Cathl