Hello everybody! This post shares a GitHub repository containing three independent FPGA accelerator implementations, each targeting a different application domain and showcasing a distinct set of hardware design strategies.
Each implementation explores a different class of ML models and preprocessing assumptions, making this repository a practical reference for anyone looking to deploy neural networks on FPGAs using the AMD AUP-ZU3 SoC.
Whether you’re getting started with hls4ml or looking to extend your existing designs, these projects cover a range of techniques that complement each other.