Please tell me why the ./make-hw.sh is failing with the error-
INFO: [HLS 200-10] Adding test bench file ‘/home/adsc/Downloads/LSTM_PYNQ/lstm/src/library/host/lstm_inference.cpp’ to the project
INFO: [HLS 200-10] Adding test bench file ‘/home/adsc/Downloads/LSTM_PYNQ/lstm/src/network/plain/W2A2/…/…/main.cpp’ to the project
INFO: [HLS 200-10] Creating and opening solution ‘/home/adsc/Downloads/LSTM_PYNQ/lstm/src/network/output/hls-syn/plain-W2A2/sol1’.
INFO: [HLS 200-10] Setting target device to ‘xc7z020clg400-1’
INFO: [SYN 201-201] Setting up clock ‘default’ with a period of 5ns.
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch CLANG as the compiler.
Compiling …/…/…/…/…/…/main.cpp in debug mode
Compiling …/…/…/…/…/…/…/library/host/lstm_inference.cpp in debug mode
Compiling …/…/…/…/…/…/plain/top.cpp in debug mode
Generating csim.exe
Makefile.rules:374: recipe for target ‘csim.exe’ failed
obj/lstm_inference.o: In function lstm_ocr_wrapper': /home/adsc/Downloads/LSTM_PYNQ/lstm/src/network/output/hls-syn/plain-W2A2/sol1/csim/build/../../../../../../../library/host/lstm_inference.cpp:37: undefined reference to InputImage::InputImage(float*, unsigned int)’
/home/adsc/Downloads/LSTM_PYNQ/lstm/src/network/output/hls-syn/plain-W2A2/sol1/csim/build/…/…/…/…/…/…/…/library/host/lstm_inference.cpp:40: undefined reference to InputImage::~InputImage()' /home/adsc/Downloads/LSTM_PYNQ/lstm/src/network/output/hls-syn/plain-W2A2/sol1/csim/build/../../../../../../../library/host/lstm_inference.cpp:40: undefined reference to InputImage::~InputImage()’
obj/lstm_inference.o: In function lstm_ocr(float*, int, char const*, float*)': /home/adsc/Downloads/LSTM_PYNQ/lstm/src/network/output/hls-syn/plain-W2A2/sol1/csim/build/../../../../../../../library/host/lstm_inference.cpp:64: undefined reference to Alphabet::Alphabet()’
/home/adsc/Downloads/LSTM_PYNQ/lstm/src/network/output/hls-syn/plain-W2A2/sol1/csim/build/…/…/…/…/…/…/…/library/host/lstm_inference.cpp:66: undefined reference to Alphabet::Init(std::string)' /home/adsc/Downloads/LSTM_PYNQ/lstm/src/network/output/hls-syn/plain-W2A2/sol1/csim/build/../../../../../../../library/host/lstm_inference.cpp:124: undefined reference to Alphabet::ReturnSymbol(unsigned int)’
/home/adsc/Downloads/LSTM_PYNQ/lstm/src/network/output/hls-syn/plain-W2A2/sol1/csim/build/…/…/…/…/…/…/…/library/host/lstm_inference.cpp:128: undefined reference to Alphabet::~Alphabet()' /home/adsc/Downloads/LSTM_PYNQ/lstm/src/network/output/hls-syn/plain-W2A2/sol1/csim/build/../../../../../../../library/host/lstm_inference.cpp:128: undefined reference to Alphabet::~Alphabet()’
obj/lstm_inference.o: In function lstm_ocr_from_file_path(char const*, char const*, float*)': /home/adsc/Downloads/LSTM_PYNQ/lstm/src/network/output/hls-syn/plain-W2A2/sol1/csim/build/../../../../../../../library/host/lstm_inference.cpp:49: undefined reference to InputImage::InputImage(std::string)’
/home/adsc/Downloads/LSTM_PYNQ/lstm/src/network/output/hls-syn/plain-W2A2/sol1/csim/build/…/…/…/…/…/…/…/library/host/lstm_inference.cpp:51: undefined reference to InputImage::~InputImage()' /home/adsc/Downloads/LSTM_PYNQ/lstm/src/network/output/hls-syn/plain-W2A2/sol1/csim/build/../../../../../../../library/host/lstm_inference.cpp:51: undefined reference to InputImage::~InputImage()’
clang++: error: linker command failed with exit code 1 (use -v to see invocation)
make: *** [csim.exe] Error 1
ERROR: [SIM 211-100] ‘csim_design’ failed: compilation error(s).
INFO: [SIM 211-3] *************** CSIM finish ***************
4
while executing
"source [lindex $::argv 1] "
(“uplevel” body line 1)
invoked from within
"uplevel #0 { source [lindex $::argv 1] } "
INFO: [Common 17-206] Exiting vivado_hls at Fri Jun 14 16:48:02 2019…
ERROR: [SIM 211-100] ‘csim_design’ failed: compilation error(s).
Error in Vivado_HLS
It has been solved thanks.
If you post a question that you then figure out the answer to, it would be helpful if you could explain what the solution was in case anyone else has this problem in future.
Cathal
1 Like
@ambarish Hi,
I have a similar problem. How do you solve it? Or can you understand my error and know how to solve it?
~/BNN-PYNQ-master/bnn/src/network$ ./make-hw.sh cnvW1A1 pynqZ1-Z2 a
Cloning into ‘xilinx-tiny-cnn’…
remote: Enumerating objects: 2600, done.
remote: Total 2600 (delta 0), reused 0 (delta 0), pack-reused 2600
Receiving objects: 100% (2600/2600), 15.69 MiB | 809.00 KiB/s, done.
Resolving deltas: 100% (1830/1830), done.
Checking connectivity… done.
Checking out files: 100% (87/87), done.
FINN hls library already cloned
Calling Vivado HLS for hardware synthesis…
****** Vivado™ HLS - High-Level Synthesis from C, C++ and SystemC v2017.4 (64-bit)
**** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
source /opt/Xilinx/Vivado/2017.4/scripts/vivado_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running ‘/opt/Xilinx/Vivado/2017.4/bin/unwrapped/lnx64.o/vivado_hls’
INFO: [HLS 200-10] For user ‘takoesl’ on host ‘takoesl-virtual-machine’ (Linux_x86_64 version 4.15.0-70-generic) on Thu Nov 28 19:22:51 CST 2019
INFO: [HLS 200-10] On os Ubuntu 16.04.6 LTS
INFO: [HLS 200-10] In directory ‘/home/takoesl/BNN-PYNQ-master/bnn/src/network/output/hls-syn’
HLS project: cnvW1A1-pynqZ1-Z2
HW source dir: /home/takoesl/BNN-PYNQ-master/bnn/src/network/cnvW1A1/hw
BNN HLS library: /home/takoesl/BNN-PYNQ-master/bnn/src/library/finn-hlslib
INFO: [HLS 200-10] Creating and opening project ‘/home/takoesl/BNN-PYNQ-master/bnn/src/network/output/hls-syn/cnvW1A1-pynqZ1-Z2’.
WARNING: [HLS 200-40] Cannot find design file ‘/home/takoesl/BNN-PYNQ-master/bnn/src/network/cnvW1A1/hw/top.cpp’
WARNING: [HLS 200-40] Cannot find test bench file ‘/home/takoesl/BNN-PYNQ-master/bnn/src/network/cnvW1A1/hw/…/sw/main_python.cpp’
INFO: [HLS 200-10] Adding test bench file ‘/home/takoesl/BNN-PYNQ-master/bnn/src/library/host/foldedmv-offload.cpp’ to the project
INFO: [HLS 200-10] Adding test bench file ‘/home/takoesl/BNN-PYNQ-master/bnn/src/library/host/rawhls-offload.cpp’ to the project
INFO: [HLS 200-10] Creating and opening solution ‘/home/takoesl/BNN-PYNQ-master/bnn/src/network/output/hls-syn/cnvW1A1-pynqZ1-Z2/sol1’.
INFO: [HLS 200-10] Setting target device to ‘xc7z020clg400-1’
INFO: [SYN 201-201] Setting up clock ‘default’ with a period of 5ns.
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch CLANG as the compiler.
Compiling …/…/…/…/…/…/…/library/host/rawhls-offload.cpp in debug mode
Compiling …/…/…/…/…/…/…/library/host/foldedmv-offload.cpp in debug mode
Generating csim.exe
Makefile.rules:374: recipe for target ‘csim.exe’ failed
ERROR: [SIM 211-102] C simulation failed, no ‘main’ function.
ERROR: [SIM 211-100] ‘csim_design’ failed: compilation error(s).
INFO: [SIM 211-3] *************** CSIM finish ***************
4
while executing
"source [lindex $::argv 1] "
(“uplevel” body line 1)
invoked from within
"uplevel #0 { source [lindex $::argv 1] } "
INFO: [Common 17-206] Exiting vivado_hls at Thu Nov 28 19:22:58 2019…
ERROR: [SIM 211-102] C simulation failed, no ‘main’ function.
ERROR: [SIM 211-100] ‘csim_design’ failed: compilation error(s).
Error in Vivado_HLS
Thank you so much!
Can you please share the answer with me ?
I am getting the same error
Hi to all,
I am trying to rebuild Hardware design GitHub - Xilinx/BNN-PYNQ: Quantized Neural Networks (QNNs) on PYNQ.
I installed Vivado and Vivado HLS 2018.2.
And ran the next commands:
pynqml@pynqml-VirtualBox:~/Downloads/BNN-PYNQ/bnn/src/network$ source /home/Xilinx/Vivado/2018.2/settings64.sh
pynqml@pynqml-VirtualBox:~/Downloads/BNN-PYNQ/bnn/src/network$ export XILINX_BNN_ROOT=~/Downloads/BNN-PYNQ/bnn/src/
pynqml@pynqml-VirtualBox:~/Downloads/BNN-PYNQ/bnn/src/network$ ./make-hw.sh cnvW1A2 ultra96 a
xilinx-tiny-cnn already cloned
FINN hls library already cloned
Calling Vivado HLS for hardware synthesis…
****** Vivado™ HLS - High-Level Synthesis from C, C++ and SystemC v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source /home/Xilinx/Vivado/2018.2/scripts/vivado_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running ‘/home/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/vivado_hls’
INFO: [HLS 200-10] For user ‘pynqml’ on host ‘pynqml-VirtualBox’ (Linux_x86_64 version 4.15.0-20-generic) on Tue May 12 16:09:27 CEST 2020
INFO: [HLS 200-10] On os Ubuntu 18.04.4 LTS
INFO: [HLS 200-10] In directory ‘/home/pynqml/Downloads/BNN-PYNQ/bnn/src/network/output/hls-syn’
HLS project: cnvW1A2-ultra96
HW source dir: /home/pynqml/Downloads/BNN-PYNQ/bnn/src//network/cnvW1A2/hw
BNN HLS library: /home/pynqml/Downloads/BNN-PYNQ/bnn/src//library/finn-hlslib
INFO: [HLS 200-10] Opening project ‘/home/pynqml/Downloads/BNN-PYNQ/bnn/src/network/output/hls-syn/cnvW1A2-ultra96’.
INFO: [HLS 200-10] Adding design file ‘/home/pynqml/Downloads/BNN-PYNQ/bnn/src//network/cnvW1A2/hw/top.cpp’ to the project
INFO: [HLS 200-10] Adding test bench file ‘/home/pynqml/Downloads/BNN-PYNQ/bnn/src//network/cnvW1A2/hw/…/sw/main_python.cpp’ to the project
INFO: [HLS 200-10] Adding test bench file ‘/home/pynqml/Downloads/BNN-PYNQ/bnn/src//library/host/foldedmv-offload.cpp’ to the project
INFO: [HLS 200-10] Adding test bench file ‘/home/pynqml/Downloads/BNN-PYNQ/bnn/src//library/host/rawhls-offload.cpp’ to the project
INFO: [HLS 200-10] Opening solution ‘/home/pynqml/Downloads/BNN-PYNQ/bnn/src/network/output/hls-syn/cnvW1A2-ultra96/sol1’.
INFO: [SYN 201-201] Setting up clock ‘default’ with a period of 3ns.
INFO: [HLS 200-10] Setting target device to ‘xczu3eg-sbva484-1-i’
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch CLANG as the compiler.
ERROR: [SIM 211-100] ‘csim_design’ failed: compilation error(s).
INFO: [SIM 211-3] *************** CSIM finish ***************
4
while executing
"source [lindex $::argv 1] "
(“uplevel” body line 1)
invoked from within
"uplevel #0 { source [lindex $::argv 1] } "
INFO: [Common 17-206] Exiting vivado_hls at Tue May 12 16:09:28 2020…
ERROR: [SIM 211-100] ‘csim_design’ failed: compilation error(s).
Error in Vivado_HLS
Please, can you please share the answer with me?
Hi to all,
finally, I resolved my problem.
I installed on virtual box Ubuntu 16.0.4.3 (as Xilinx recommends for Vivado 2018.2).
I installed Vivado HLx 2018.2 WebPACK (BNN PYNQ tested with this version).
The installation path is /opt/Xilinx.
And ran the next commands:
pynqml@pynqml-VirtualBox:~/Downloads/BNN-PYNQ/bnn/src/network$ source /opt/Xilinx/Vivado/2018.2/settings64.sh
pynqml@pynqml-VirtualBox:~/Downloads/BNN-PYNQ/bnn/src/network$ export XILINX_BNN_ROOT=~/Downloads/BNN-PYNQ/bnn/src/
pynqml@pynqml-VirtualBox:~/Downloads/BNN-PYNQ/bnn/src/network$ ./make-hw.sh cnvW1A2 ultra96 a
And after a long time, I rebuild the project.
The previously I worked on Ubuntu 18.0.4.2 and Vivado has been installed as Vivado HL Design Edition in /home/Xilinx.
I hope this helps.
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