Hello,
I am developing a system using the PYNQ Z2 (based on Zynq-7000 SoC) and PMOD AD1 (12-bit, SPI interface) to sample real-time voltage, perform a 8192-point FFT in the PL, and then detect specific frequency components (e.g., 40kHz and 80kHz) to map them to a bit (0 or 1). The final result will be read via AXI GPIO from the PS (Python).
(vivado 2023.1)
Current Setup (Vivado Block Diagram):
- ADC Module (Verilog):
Receives 12-bit samples from the PMOD AD1 via SPI. - FFT IP (Xilinx XFFT):
8192-point FFT, configured in real-input mode with an AXI4‑Stream interface. - Frequency Detector IP (Verilog):
Accumulates and compares the energy in the FFT results (Real + Imag) within the bin ranges corresponding to 40kHz and 80kHz (±WINDOW) and outputs a freq_bit (0 or 1). - AXI GPIO:
Exposes the freq_bit and debugging signals (sum_40 and sum_80) to the PS, which are then read in Python.
Debugging Results and Issues:
- When reading via AXI GPIO in Python, the values for sum_40, sum_80, and freq_bit alternate between very large values (≈4.29×10^9) and 0.
- It appears that the system is not reliably detecting the alternating 40kHz and 80kHz signals every second.
- With an FFT length of 8192 and a sampling rate of 500kSPS, the bin resolution is approximately 61Hz, which raises concerns about whether it is sufficient to distinguish 40kHz and 80kHz accurately.
Questions:
- DMA Usage:
If I only need to pass freq_bit to the PS, is it sufficient to use AXI GPIO without DMA, or is using DMA more appropriate? - Bit Mapping Criteria:
How should I compare the energy in the 40kHz and 80kHz bands to set a threshold (margin) for mapping? Is it common to use a criterion such as “if the 80kHz energy is a certain multiple greater than the 40kHz energy, then output 1”? - Additional Considerations:
When harmonics or noise are present, is a simple bin comparison enough, or should additional filtering (e.g., Goertzel, FIR/IIR) be applied?
Thank you for your help.