AXI DMA with FFT and PYNQ-Z2

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1

I am using the PYNQ-Z2 Board and made a simple Design with Vivado. Also I am debuging my design with ILA Cores via the Micro USB Connection. I just want to peform a simple FFT with a width of 8 samples.

This is the jupyter python code for transferring and receiving the data:

xlnk = Xlnk()
in_buffer = allocate(shape=(512,), dtype=np.int32) #shape=(n,)
out_buffer = allocate(shape=(512,), dtype=np.int32) #shape=(n,)

Copy the samples to the in_buffer

np.copyto(in_buffer, arr)

Trigger the DMA transfer and wait for the result

dma.sendchannel.transfer(in_buffer)
dma.recvchannel.transfer(out_buffer)
dma.sendchannel.wait()
dma.recvchannel.wait()

The programm stops at at dma.recvchannel.wait(). Stopping the programm results in the following error:

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When I comment the dma.recvchannel.wait() command debugging shows that there ist data coming out the FFT IP but the S2MM DMA Inteface is inactive:

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Does anybody know what I am doing wrong?
Design.pdf (91.2 KB)

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2

Hi,

Have you tried using an AXI-Stream Data FIFO on the read and write channels of the DMA? I made a simply passthrough example with Zynq → DMA(read) → FIFO → DMA(write) → Zynq and was able to stream data continously. In my experience, the FIFO is necessary to prevent the DMA from stalling.

I tried to recreate your project, but wasn’t sure how you removed the S_AXIS_CONFIG port from the FFT IP. How did you do that?

rn

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3

I was having the same confusion too. Your FFT IP has a config port which you have not connected - I am not sure what you are doing with that port.

Also, for your block design, the interconnect ARESETN pin should be connected to the interconnect_aresetn of the reset block.

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But don’t get me wrong - this connection error is not the main reason why you got the hanging problem.

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4

It looks like the TREADY signal has dropped off your FFT block which looks odd. If this is really the case, this might be why you see problems.
If you think this is the problem, you could try regenerating the design, or removing, and adding the FFT block again.

Cathal

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5

Thank you very much. The problem seems to be that I configured the FFT IP as “Real Time”. If you do so the block doesn’t have a TREADY at the MAXIS_DATA port. Now I configured the block as “Non Real Time” and it works also withe the dma.recvchannel.wait() command.

Also I gave some constants for the S_AXIS_CONFIG port of the FFT block.

Again thank you very much!

FFT.pdf (81.1 KB)

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6

Can i ask you which values did you put inside the constant for the S_AXIS_CONFIG of the fft block? I am configuring my module following the documentation, but i can’t understand what does it expect in those 7 bits of t_data

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