Hello, for transfering a list of data from PS to PL, An AXI interface maybe needed.st
step 1 from ug871,there is a sample on design axi interface IP.
step2: could we use xlinl or buffer directly like this tutorial on jupytor:PYNQ-HelloWorld/resizer_pl.ipynb at master · Xilinx/PYNQ-HelloWorld · GitHub
Hi, I’m just a fellow Pynq user so I won’t have all the answers but recently I spent a bit of time figuring out how to set this up.
First, I recommend giving this a read: Understanding AXI Addressing
It goes over normal AXI transactions and what you should expect your waveforms to look like.
If that makes sense to you then from there I recommend this video as for how to actually setup an AXI interface in Vivado: Generating custom AXI4-Stream IP core using Xilinx Vivado - YouTube
Hopefully this helps. I know this stuff can be a bit convoluted to figure out from scratch so good luck!
