PYNQ Version: v3.1
Boards: PYNQ-Z1 and Custom Boards (Zynq-7000)
I am using the PYNQ-Z1 to learn PYNQ. When the system boots, the PL configuration is automatically loaded. I suspect this is due to the overlay execution in boot.py.
My first question is: Since the bitstream has already been loaded, can it be used directly in user programs without reloading it? Reloading the same bitstream file seems cumbersome. How can this be achieved? Would the following approach work?
base = Overlay(“base.bit”, download=False) # The Overlay is instantiated, but the bitstream is not downloaded to the PL.
I also want to use the Dynamic Function eXchange (DFX) feature on a custom hardware platform. Since the ETH controller is routed out via EMIO and the “gmii to rgmii” IP is used in the PL, I hope to load the static bitstream file immediately upon power-on so that the network is available when Linux starts. This seems related to the FPGA_MANAGER_${BOARD} setting during image construction. According to the official documentation: Set to 0 to disable the FPGA Manager; users may wish to download the bitstream at boot time to enable certain board components as early as possible. Set to 1 or leave undefined to enable the FPGA Manager. In this case, the bitstream will be downloaded later in the user application; this is the default behavior of PYNQ because we want users to be able to download any bitstream after boot.
My second question is: How can I achieve both downloading the bitstream at boot time to enable certain board components as early as possible, and still be able to load partial reconfiguration files in user programs using overlay.pr_download(‘block_0’, ‘rm_0_partial.bit’) after boot?
Hi @Giraffe,
Welcome to the PYNQ community.
My first question is: Since the bitstream has already been loaded, can it be used directly in user programs without reloading it? Reloading the same bitstream file seems cumbersome. How can this be achieved? Would the following approach work?
base = Overlay(“base.bit”, download=False) # The Overlay is instantiated, but the bitstream is not downloaded to the PL.
Yes, this works. Why do you say this feels cumbersome?
How can I achieve both downloading the bitstream at boot time to enable certain board components as early as possible, and still be able to load partial reconfiguration files in user programs using overlay.pr_download(‘block_0’, ‘rm_0_partial.bit’) after boot?
Wouldn’t loading with boot.py work for you? For more support on this question, you may be better off asking in the Xilinx forums.
Mario
Thank you for your reply.
When there are functions in the static logic that need to remain running — for example, network connections routed to the PL — I understand that the static logic does not need to be reloaded. Perhaps boot.py could work, but I’m not entirely sure, and I’m also exploring earlier loading methods.