How to send arrays via DMA

I am trying to create custom IP using HLS with PYNQ Z2. I have function like this
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but i don’t understand how to make the correct IP design to make it work.
I tried a lot of different options of connection, but it fails with code like this:

in_buffer = xlnk.cma_array(shape=(num_of_input_bytes,),dtype = np.uint8) #uint8
out_buffer = xlnk.cma_array(shape=(num_of_input_bytes,),dtype = np.uint8)

input_bytes = np.array( bytearray(input_bytes))

mmio.write(16, num_of_input_bytes ) 
while(not( & 0x4)) # infinite loop

How should I connect my encrypt module and dma?
Thank you

What PYNQ version are you using? What Vivado/HLS version?

Can you share an image of your block design? What steps have you tried?

Pynq Z2, image v 2.4, Vitis HLS 2021.1, Vivado 2021.1.
Now it looks like this

I just typed “Make auto connection”. I tried to connect using this example AES_implementations/PZ1CipherStreamII2.png at master · hplp/AES_implementations (
but no result.
What steps should I do to make it work?

I recommend you to watch this tutorial on how to create an overlay with an AXI4-Stream FIR IP. Most of the concepts are transferable to your design.

Thank you! One last question please.
Now i have pragmas like this:

#pragma HLS INTERFACE s_axilite port=Data
#pragma HLS INTERFACE s_axilite port=Data_out
#pragma HLS INTERFACe s_axilite port=return

and now have s_axi_control port. But FIR have S_AXIS_DATA and M_AXIS_DATA:
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What pragmas should I use to make two AXI ports?

The interfaces are already AXI4-Stream. If you want to make them AXI4-MM use something like this

#pragma HLS INTERFACE m_axi port=Data
#pragma HLS INTERFACE m_axi port=Data_out

Didn’t work. Here is a comparison
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Yes, it did work. AXI4-MM interfaces were generated.

If you want to generate AXI4-Stream interfaces you need to change your code, for instance you cannot use arrays if you want to implement streaming interfaces.

You will have to do something like this

Got it, thank you