PYNQ Z2 with [v3.0.1]
I had asked this question before but had gotten no replies so thought would post this again. Even if someone could point me to the right direction, your help will be genuinely appreciated.
I am very new to FPGA programming and this is the first board I am using. For the past month, I have been trying to connect an Arduino shield with my PYNQ Z2 board. I have a SparkFun CANBUS shield(CAN-BUS Shield - DEV-13262 - SparkFun Electronics) and my goal is to connect it to PYNQ Z2. Can anyone guide me on how to go about this? I have tried a lot of things but have made no progress.
I also have another Can bus which is for raspberry pi (PiCAN2 - Duo CAN-Bus Board for Raspberry Pi 2) I have tried this as well and no luck. Can anyone help me out with either one but preferably the raspberry pi one?
Basically, I connected both and tried a lot to program them or at least connect them to the PYNQ z2. If I am able to at least connect and detect the picanduo board, it would be amazing.
Any help will be appreciated
Thnaks!
1 Like
This may not be well supported with PYNQ.
Zynq has a hard CAN bus IP. You could try enable it and route it via EMIO to the FPGA pins. I haven’t worked with this IP so I’m not sure if you can do this.
If you can build a design like this, you could then try to program it, most likely from C rather than Python.
You would need to be familiar with Vivado, and writing software for Zynq (e.g. using Vitis to build the software app).
Xilinx also have paid IP, but this is probably out of scope for a hobbyist project which I think this is.
Cathal
@technical @cathalmccabe
Cath proposed CAN Bus IP is over cost and completely waste of memory even you undergo an evaluation you will see it is not worth.
Two great methods are suggested, but no matter which method Cath also did not mention the need of TRANSCEIVERS IC and termination resistor, which is a must !!!
Method 1 ZYNQ ARM itself have core CAN bus just add front-end IC and put can mio or emio + CAN bus TRANSCEIVERS:
Method 2: opencore SJA1000 HDL free design can be download.
Add wishbone to AXI interface conversion and increase the data buffer.
Had tried myself and working great on Vitis almost 4 years ago.
All you need is control via general AXI-register Xil_In32/ Xil_Out32 read/write.
https://opencores.org/projects/can
Easy
ENJOY~
