I am trying to interface my PYNQ-Z2 board with LVGL with ILI9341 SPI controller LCD. There is driver in mainstream kernel for this chip, so probably it could be used with DRM as a regular frame-buffer.
- First approach would be using AXI SPI interface, but then one should develop a wrapper for every LVGL call to translate to PYNQ SPI call. Also no (easy) DRM with this approach. But maybe higher SPI clock rates could be obtained than PS SPI? Could it be reasonable to make access AXI SPI as regular spidev in Linux PS?
- Second approach: Zynq 7020 PS has SPI controller. If I understand correctly, SPI should be enabled in Vivado Zynq IP, then signals needs to be routed to physical pins, and then Linux should detect it. Maybe dynamic device tree overlays would be needed.
- Max SPI clock speed with EMIO is 25 MHz, with MIO - 50 MHz [ug585] (AMD Adaptive Computing Documentation Portal). If I understand correctly, MIO are fixed pins and location can’t be changed so they can’t be reused with different purpose in PYNQ? (Actually I need to disable USB to make MIO available for SPI)
What approach could you recommend?