I’ve made an image processing IP core using Vitis High Level Synthesis, that receives and image from AXI-Stream, processes the image and then outputs some result 1D arrays through the AXI4 protocol, using the interface m_axi directive and the memcpy function. Everything works correctly, I’ve done the jupyter notebook and the results are the ones I expect. Now, I would like to know what would be the best practice to signal the Zynq PS that the result arrays are already in the DRAM so that they can be used by the CPU.
Should I use interrupts? If so, what changes should I do in HLS code/Vivado design/jupyter notebook?
My goal is that the PS starts using the result arrays as soon as they are available on the DRAM.