Key error when loading overlay

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Thank you for your advice! I reconstruct my project like this:

image
image1548×1042 140 KB

I package my PL part as an IP “eva_pl”. And in order to assign the address for AHB, when packaging I pack my AHB interface and create an address block for it. So I can assign addresses in BD.

But I get the following error when loading overlay:

---------------------------------------------------------------------------
UnexpectedPortTypeError                   Traceback (most recent call last)
Input In [3], in <cell line: 3>()
      1 # from pynq import allocate, Overlay
      2 # import pdb; pdb.set_trace()
----> 3 eva=Overlay("/home/root/jupyter_notebooks/eva/EVA.xsa")

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/overlay.py:319, in Overlay.__init__(self, bitfile_name, dtbo, download, ignore_version, device, gen_cache)
    315 super().__init__(bitfile_name, dtbo, partial=False, device=device)
    317 self._register_drivers()
--> 319 self.device.set_bitfile_name(self.bitfile_name)
    320 self.parser = self.device.parser
    322 self.ip_dict = (
    323     self.gpio_dict
    324 ) = (
    325     self.interrupt_controllers
    326 ) = self.interrupt_pins = self.hierarchy_dict = dict()

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/device.py:118, in Device.set_bitfile_name(self, bitfile_name)
    116 def set_bitfile_name(self, bitfile_name: str) -> None:
    117     self.bitfile_name = bitfile_name
--> 118     self.parser = self.get_bitfile_metadata(self.bitfile_name)
    119     self.mem_dict = self.parser.mem_dict
    120     self.ip_dict = self.parser.ip_dict

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/embedded_device.py:690, in EmbeddedDevice.get_bitfile_metadata(self, bitfile_name, partial)
    689 def get_bitfile_metadata(self, bitfile_name:str, partial:bool=False):
--> 690     parser = _get_bitstream_handler(bitfile_name).get_parser(partial=partial)
    691     if parser is None:
    692         raise RuntimeError("Unable to find metadata for bitstream")

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/embedded_device.py:268, in BitstreamHandler.get_parser(self, partial)
    266     parser = XclBin(xclbin_data=xclbin_data)
    267 elif is_xsa:
--> 268     parser = RuntimeMetadataParser(Metadata(input=self._filepath))
    269     if xclbin_data is None:
    270         xclbin_data = _create_xclbin(parser.mem_dict)

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/metadata.py:41, in Metadata(input)
     39     return HwhFrontend(_hwhfile=input)
     40 elif str(input).endswith(".xsa"):
---> 41     return XsaFrontend(input=input) 
     42 elif str(input).endswith(".json"):
     43     return JsonFrontend(input=input)

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/xsa_frontend.py:24, in XsaFrontend(input)
     22 xsa = XsaParser(input)
     23 xsa.load_bdc_metadata()
---> 24 md = HwhFrontend(_hwhfile=xsa.defaultHwhPaths[0])
     25 md.ext["xsa"] = XsaObjectExtension(xsa=xsa)
     26 for b in md.blocks.values():

File <string>:25, in __init__(self, name, type, generic_type, _parent, _children, ref, ext, _timestamp, hierarchy_name, ports, parameters, blocks, modules, busses, _hierarchies, _hwhfile, _element_tree, _root, _logical2physical_portmap, _physical2logical_portmap, _logical2physical_extern_pm, _physical2logical_extern_pm)

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:219, in HwhFrontend.__post_init__(self)
    207 """
    208 Performs the parsing of the hwh into the metadata model
    209 * checks to see if the hwhfile is an XML string or a
   (...)
    216 * Performs a connectivity pass
    217 """
    218 if self._hwhfile != "":
--> 219     self.parse()

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:240, in HwhFrontend.parse(self)
    237 self._construct_logical2physical_extern_pm()
    238 self._create_external_ports()
--> 240 self.resolve_addressing()
    241 self.connect_signals()
    243 self.refresh()

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:611, in HwhFrontend.resolve_addressing(self)
    604 def resolve_addressing(self) -> None:
    605     """
    606     For all the subordinate ports in the design and manager ports
    607     grab all the addressing information
    608     WARNING: This should only be called after all the cores and ports
    609     have been populated.
    610     """
--> 611     self._resolve_subordinate_addressing()
    612     self._populate_subordinate_regmap()
    613     self._resolve_manager_address_maps()

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:473, in HwhFrontend._resolve_subordinate_addressing(self)
    471     port.range = (int(i.get("HIGHVALUE"), 16) - port.baseaddr) + 1
    472 else:
--> 473     raise UnexpectedPortTypeError(
    474         f"Expected {port.ref} to be SubordinatePort when assigning base address"
    475     )

UnexpectedPortTypeError: Expected EVA:eva_pl_0[block]:S_AHB[port] to be SubordinatePort when assigning base address

But if I don’t create the address block for S_AHB, it will show incomplete path in BD address editor. What is the right way to control AHB BUS in pynq?

If you don’t mind I’d like to ask another question about the bram crontroller. The bram in “eva_pl” is 512-bit width, but the AXI_HPM_FPD is 128bit width at most, so I use a smartconnect to convert it. Can I use these simple codes to write and read the first row in my bram?

bram=overlay.axi_bram_ctrl_0
for i in range(16):
    bram.write(i*4, data[i])
for i in range(16):
    result[i]=bram.read(i*4)
    print(result[i])
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