Hi,
I’m trying to redo the “PYNQ-Helloworld” example from scratch. Compiling the resize HLS code from Github is OK, and I can generate the IP.
In Vivado IP Integrator, I have connected the IP to an axi_interconnect block and then to a s_axi_hp0_ffd of the UltraScale+. But I’m not sure this is how it has been done in the “PYNQ-Helloworld” example and if this is the correct way to do it. It would be very helpful if I could have the Vivado part of this example or at least a picture of the IP Integrator showing the blocks used and the connections. I’m also surprised that IP Integrator has not generated any DDR connection as it does usually with Zynq projects.
Regards