Kria PYNQ DMA connect problem

Support
1

Hi everyone, I have made a stream-based vector addition HLS ip using VITIS UNIFIED. However, when I connect IP to DMA in VIVADO, I always get the following critical errors:

[BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /vector_add_top_0/A_stream(4) and /axi_dma_0/M_AXIS_MM2S(8)

[BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /vector_add_top_0/B_stream(4) and /axi_dma_0/M_AXIS_MM2S(8)

I carefully checked the Settings of the DMA module according to the DMA tutorial and found that its DATA_NUM_BYTES was automatically set to 8 and could not be changed.

Although I can ignore these two pieces of information and generate a.bit file, I get stuck when PYNQ calls the ip:

dma1.sendchannel.wait()

Is this caused by an error in VIVADO? Or is there some other reason? What can I do to use this IP properly?

屏幕截图 2025-03-06 205829
屏幕截图 2025-03-06 2058291609×757 77 KB

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屏幕截图 2025-03-06 2058061816×1444 89.2 KB

#include "vector.h"
#define MAX_SIZE 50000

void vector_add_top(
    hls::stream<ap_axis<32, 0, 0, 0>>& A_stream, // AXI Stream with TLAST
    hls::stream<ap_axis<32, 0, 0, 0>>& B_stream, // AXI Stream with TLAST
    hls::stream<ap_axis<32, 0, 0, 0>>& C_stream, // AXI Stream with TLAST
    int size
) {
#pragma HLS INTERFACE mode=s_axilite port=return bundle=control
#pragma HLS INTERFACE mode=s_axilite port=size bundle=control
#pragma HLS INTERFACE mode=axis port=A_stream
#pragma HLS INTERFACE mode=axis port=B_stream
#pragma HLS INTERFACE mode=axis port=C_stream

    //
    ap_axis<32, 0, 0, 0> A_val, B_val, C_val;

    // 
    for (int i = 0; i < size; i++) {
#pragma HLS PIPELINE II=1
        //  A_stream 
        A_stream.read(A_val);
        //  B_stream 
        B_stream.read(B_val);

        // 
        C_val.data = A_val.data + B_val.data;

        //  TLAST 
        if (i == size - 1) {
            C_val.last = 1; // 
        } else {
            C_val.last = 0;
        }

        // C_stream
        C_stream.write(C_val);
    }
}
2

The warning message is for axi_dma_0, but your screenshot is for axi_dma_1

A mismatch in the number of bits in TDATA can cause this problem you are seeing.

3

Thank you for your reply. Since my IP sets variable as 32-bit stream, I changed the Stream Data Width of dma 0&1 from 64 to 32. The previous warning disappeared, but a new warning appears here.

屏幕截图 2025-03-07 215859
屏幕截图 2025-03-07 2158591807×1416 88 KB

validate_bd_design
WARNING: [BD 41-1629] Slave segment </zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM> is excluded from all addressing paths.
Excluding slave segment /zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM from address space /axi_dma_0/Data_MM2S.
Excluding slave segment /zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM from address space /axi_dma_0/Data_S2MM.
Excluding slave segment /zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM from address space /axi_dma_1/Data_MM2S.
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/axi_smc_1/S00_AXI' to master interface '/axi_smc_1/M00_AXI'. This will be used by smartconnect on path for routing.
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/axi_smc_1/S01_AXI' to master interface '/axi_smc_1/M00_AXI'. This will be used by smartconnect on path for routing.
INFO: [BD 5-943] Reserving offset range <0x0000_0000 [ 2G ]> from slave interface '/axi_smc_1/S02_AXI' to master interface '/axi_smc_1/M00_AXI'. This will be used by smartconnect on path for routing.
INFO: [xilinx.com:ip:smartconnect:1.0-1] twice_axi_smc_1_2: SmartConnect twice_axi_smc_1_2 is in High-performance Mode.
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_HP0_FPD(1) and /axi_smc_1/M00_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_HP0_FPD(1) and /axi_smc_1/M00_AXI(0)
validate_bd_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2098.438 ; gain = 0.000
4

I think this is safe to ignore for now.