Hi everyone,
I am working with a Xilinx Kria KV260 with PYNQ version 3.0.1. I have created a bitstream that is functional and it is works correctly (both simulation and on the FPGA), but after I loaded a second bitstream and then again the first one the design stopped working, indeed, the FPGA responds with wrong result and each time it is different, even if my desgin should always produce the same result.
The accelerator is connected to the PS through an AXI stream interface, any possible idea of why the system suddently stopped working? Even after a power reset of the board the results are wrong, so i tryed on another board but after the same procedure always my second board broke.
It can be caused from my PYNQ software?
To download the bitstream i proceed in the following way:
- PL.reset()
- design = Overlay(bitsream.bit)
- PL.reset() # again
Hi @Christian-Conti,
Welcome to the PYNQ community.
The accelerator is connected to the PS through an AXI stream interface
The PS does not have stream interfaces. Are you using a DMA?
Does the design work properly when you do not load a different overlay?
Mario
Yes, my design is connected to the DMA and Vivado’s IP.
After this “incident,” the design no longer works properly, even after disconnecting the board from AC power and reconnecting it after some time. It still doesn’t function correctly.
I’m unsure if there’s a command in PYNQ that can clear all cached information or reset the system in some way.
Christian
Ok, I see. I think I see the problem now. You are not supposed to run PL.reset() after you download the overlay. Overlay(bitstream.bit)
Mario
Hi, thanks for the suggestion, unfortunately I have removed it and the issue still persist.
Even after removing it and reboot the board.
Christian
Can you please provide more information about what the overlay does?
